我在主程序中初始化:CpuToClaParam1=5,
结果运行完CLA程序，得到的ClaToCpuParam1=1，而不是6呢？
#pragma DATA_SECTION(CpuToClaParam1,"CpuToCla1MsgRAM");
float CpuToClaParam1;
#pragma DATA_SECTION(ClaToCpuParam1,"Cla1ToCpuMsgRAM");
float ClaToCpuParam1;
extern uint32_t Cla1ProgRunStart, Cla1ProgLoadStart, Cla1ProgLoadSize;
extern uint32_t Cla1ConstRunStart, Cla1ConstLoadStart, Cla1ConstLoadSize;
__attribute__((interrupt)) void Cla1Task1( void );
void CfgClaMemory(void)
{
///复位CLA将要使用的这段内存
EALLOW;
MemCfgRegs.LSxMSEL.bit.MSEL_LS0 = 0U;
MemCfgRegs.LSxMSEL.bit.MSEL_LS3 = 0U;
MemCfgRegs.LSxMSEL.bit.MSEL_LS4 = 0U;
MemCfgRegs.LSxMSEL.bit.MSEL_LS7 = 0U;
Cla1Regs.MCTL.bit.HARDRESET=1;
NOP;
NOP;
NOP;
EDIS;
///CLA将要使用的这段内存复位完成
// 从Flash中将CLA程序拷贝到CLA运行内存中
memcpy((uint32_t *)&Cla1ProgRunStart, (uint32_t *)&Cla1ProgLoadStart,(uint32_t)&Cla1ProgLoadSize);
memcpy((uint32_t *)&Cla1ConstRunStart, (uint32_t *)&Cla1ConstLoadStart,(uint32_t)&Cla1ConstLoadSize);
EALLOW;
//Initialize and wait for CLA1ToCPUMsgRAM
MemCfgRegs.MSGxINIT.bit.INIT_CLA1TOCPU = 1;
while(MemCfgRegs.MSGxINITDONE.bit.INITDONE_CLA1TOCPU != 1){};
//Initialize and wait for CPUToCLA1MsgRAM
MemCfgRegs.MSGxINIT.bit.INIT_CPUTOCLA1 = 1;
while(MemCfgRegs.MSGxINITDONE.bit.INITDONE_CPUTOCLA1 != 1){};
//
// Select CLA as the master of RAMLS2, RAMSL3
//
MemCfgRegs.LSxMSEL.bit.MSEL_LS0 = 1U;
MemCfgRegs.LSxMSEL.bit.MSEL_LS3 = 1U;
MemCfgRegs.LSxMSEL.bit.MSEL_LS4 = 1U;
MemCfgRegs.LSxMSEL.bit.MSEL_LS7 = 1U;
//
// CLA Program will reside in RAMLS3-RAMLS5 and data in RAMLS2
// CMD 文件里分配RAMLS2时必须是一整块，不能分割
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS0 = 1U;
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS3 = 1U;
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS4 = 1U;
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS7 = 0U;
EDIS;
}
void InitClaCpu(void)
{
EALLOW;
Cla1Regs.MVECT1 = (uint16_t)&Cla1Task1;
__asm(" RPT #7 || NOP");
DmaClaSrcSelRegs.CLA1TASKSRCSEL1.bit.TASK1 = 0;//配置CLA中断方式为软件触发
Cla1Regs.MIER.all = M_INT1;//使能中断
Cla1Regs.MCTL.bit.IACKE = 1;
IER |= (M_INT11);
EDIS;
}
void main(void)
{
//Initialize device clock and peripherals
InitSysCtrl();
// Initialize PIE and clear PIE registers. Disables CPU interrupts.
DINT;
InitPieCtrl();
IER = 0x0000;
IFR = 0x0000;
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
InitPieVectTable();
// Initialize GPIO and configure the GPIO pin as a push-pull output
StartCpuTimer0();
DEVICE_DELAY_US(200000);//0.01S 延时防止硬件过流保护
CpuToClaParam1=5;//初始化参数
CfgClaMemory();
InitClaCpu();
EINT;
ERTM;
Cla1ForceTask1();
for(;;)
{
}
}
CLA程序:
extern float CpuToClaParam1;
extern float ClaToCpuParam1;
__attribute__((interrupt)) void Cla1Task1(void)
{
__mdebugstop();
//在这里面编写要执行的程序
ClaToCpuParam1=CpuToClaParam1+1;//参数传递测试
//__mdebugstop();
}
CMD文件:
MEMORY
{
PAGE 0 :
/* BEGIN is used for the "boot to SARAM" bootloader mode */
BEGIN : origin = 0x080000, length = 0x000002
RAMM0 : origin = 0x0000F6, length = 0x00030A
RAMLS0 : origin = 0x008000, length = 0x000800
RAMLS3 : origin = 0x009800, length = 0x000800
RAMLS4 : origin = 0x00A000, length = 0x000800
//RAMLS7 : origin = 0x00B800, length = 0x000800
RESET : origin = 0x3FFFC0, length = 0x000002
/* Flash sectors */
/* BANK 0 */
FLASH_BANK0_SEC0 : origin = 0x080002, length = 0x000FFE /* on-chip Flash */
FLASH_BANK0_SEC1 : origin = 0x081000, length = 0x001000 /* on-chip Flash */
FLASH_BANK0_SEC2 : origin = 0x082000, length = 0x001000 /* on-chip Flash */
FLASH_BANK0_SEC3 : origin = 0x083000, length = 0x001000 /* on-chip Flash */
FLASH_BANK0_SEC4 : origin = 0x084000, length = 0x001000 /* on-chip Flash */
FLASH_BANK0_SEC5 : origin = 0x085000, length = 0x001000 /* on-chip Flash */
FLASH_BANK0_SEC6 : origin = 0x086000, length = 0x001000 /* on-chip Flash */
FLASH_BANK0_SEC7 : origin = 0x087000, length = 0x001000 /* on-chip Flash */
FLASH_BANK0_SEC8 : origin = 0x088000, length = 0x001000 /* on-chip Flash */
FLASH_BANK0_SEC9 : origin = 0x089000, length = 0x001000 /* on-chip Flash */
FLASH_BANK0_SEC10 : origin = 0x08A000, length = 0x001000 /* on-chip Flash */
FLASH_BANK0_SEC11 : origin = 0x08B000, length = 0x001000 /* on-chip Flash */
FLASH_BANK0_SEC12 : origin = 0x08C000, length = 0x001000 /* on-chip Flash */
FLASH_BANK0_SEC13 : origin = 0x08D000, length = 0x001000 /* on-chip Flash */
FLASH_BANK0_SEC14 : origin = 0x08E000, length = 0x001000 /* on-chip Flash */
FLASH_BANK0_SEC15 : origin = 0x08F000, length = 0x001000 /* on-chip Flash */
/* BANK 1 */
FLASH_BANK1_SEC0 : origin = 0x090000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC1 : origin = 0x091000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC2 : origin = 0x092000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC3 : origin = 0x093000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC4 : origin = 0x094000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC5 : origin = 0x095000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC6 : origin = 0x096000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC7 : origin = 0x097000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC8 : origin = 0x098000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC9 : origin = 0x099000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC10 : origin = 0x09A000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC11 : origin = 0x09B000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC12 : origin = 0x09C000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC13 : origin = 0x09D000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC14 : origin = 0x09E000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC15 : origin = 0x09F000, length = 0x000FF0 /* on-chip Flash */
// FLASH_BANK1_SEC15_RSVD : origin = 0x09FFF0, length = 0x000010 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
PAGE 1 :
BOOT_RSVD : origin = 0x000002, length = 0x0000F1 /* Part of M0, BOOT rom will use this for stack */
RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */
// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
RAMLS1 : origin = 0x008800, length = 0x000800
RAMLS2 : origin = 0x009000, length = 0x000800
RAMLS5 : origin = 0x00A800, length = 0x000800
RAMLS6 : origin = 0x00B000, length = 0x000800
RAMLS7 : origin = 0x00B800, length = 0x000800
RAMGS0 : origin = 0x00C000, length = 0x002000
RAMGS1 : origin = 0x00E000, length = 0x002000
RAMGS2 : origin = 0x010000, length = 0x002000
RAMGS3 : origin = 0x012000, length = 0x001FF8
// RAMGS3_RSVD : origin = 0x013FF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
CLA1_MSGRAMLOW : origin = 0x001480, length = 0x000080
CLA1_MSGRAMHIGH : origin = 0x001500, length = 0x000080
}
SECTIONS
{
.cinit : > FLASH_BANK0_SEC1, PAGE = 0, ALIGN(4)
.text : >>FLASH_BANK0_SEC2 | FLASH_BANK0_SEC3, PAGE = 0, ALIGN(4)
codestart : > BEGIN PAGE = 0, ALIGN(4)
.stack : > RAMM1 PAGE = 1
.switch : > FLASH_BANK0_SEC1, PAGE = 0, ALIGN(4)
#if defined(__TI_EABI__)
.init_array : > FLASH_BANK0_SEC1, PAGE = 0, ALIGN(4)
.bss : > RAMLS5, PAGE = 1
.bss:output : > RAMLS5, PAGE = 1
.bss:cio : > RAMLS5, PAGE = 1
.data : > RAMLS6, PAGE = 1
.sysmem : > RAMLS6, PAGE = 1
.const : > FLASH_BANK0_SEC4, PAGE = 0, ALIGN(4)
#else
.pinit : > FLASH_BANK0_SEC1, PAGE = 0, ALIGN(4)
.ebss : >>RAMLS5 | RAMLS6, PAGE = 1
.esysmem : > RAMLS6, PAGE = 1
.cio : > RAMLS5, PAGE = 1
.econst : > FLASH_BANK0_SEC4, PAGE = 0, ALIGN(4)
#endif
ramgs0 : > RAMGS0, PAGE = 1
ramgs1 : > RAMGS1, PAGE = 1
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
dclfuncs : > FLASH_BANK0_SEC1, PAGE = 0, ALIGN(4)
#if defined(__TI_EABI__)
/* CLA specific sections */
Cla1Prog : LOAD = FLASH_BANK0_SEC4,
RUN = RAMLS0,
LOAD_START(Cla1ProgLoadStart),
RUN_START(Cla1ProgRunStart),
LOAD_SIZE(Cla1ProgLoadSize),
PAGE = 0, ALIGN(4)
#else
/* CLA specific sections */
Cla1Prog : LOAD = FLASH_BANK0_SEC4,
RUN = RAMLS0,
LOAD_START(_Cla1ProgLoadStart),
RUN_START(_Cla1ProgRunStart),
LOAD_SIZE(_Cla1ProgLoadSize),
PAGE = 0, ALIGN(4)
#endif
Cla1ToCpuMsgRAM : > CLA1_MSGRAMLOW, PAGE = 1
CpuToCla1MsgRAM : > CLA1_MSGRAMHIGH, PAGE = 1
#if defined(__TI_EABI__)
.TI.ramfunc : LOAD = FLASH_BANK0_SEC1,
RUN = RAMLS4
LOAD_START(RamfuncsLoadStart),
LOAD_SIZE(RamfuncsLoadSize),
LOAD_END(RamfuncsLoadEnd),
RUN_START(RamfuncsRunStart),
RUN_SIZE(RamfuncsRunSize),
RUN_END(RamfuncsRunEnd),
PAGE = 0, ALIGN(4)
#else
.TI.ramfunc : LOAD = FLASH_BANK0_SEC1,
RUN = RAMLS4
LOAD_START(_RamfuncsLoadStart),
LOAD_SIZE(_RamfuncsLoadSize),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
RUN_SIZE(_RamfuncsRunSize),
RUN_END(_RamfuncsRunEnd),
PAGE = 0, ALIGN(4)
#endif
.scratchpad : > RAMLS7, PAGE = 1
.bss_cla : > RAMLS7, PAGE = 1
Cla1DataRam : > RAMLS7, PAGE = 1
cla_shared : > RAMLS7, PAGE = 1
CLADataLS1 : > RAMLS7, PAGE = 1
#if defined(__TI_EABI__)
.const_cla : LOAD = FLASH_BANK0_SEC2,
RUN = RAMLS3,
RUN_START(Cla1ConstRunStart),
LOAD_START(Cla1ConstLoadStart),
LOAD_SIZE(Cla1ConstLoadSize),
PAGE = 0, ALIGN(4)
#else
.const_cla : LOAD = FLASH_BANK0_SEC2,
RUN = RAMLS3,
RUN_START(_Cla1ConstRunStart),
LOAD_START(_Cla1ConstLoadStart),
LOAD_SIZE(_Cla1ConstLoadSize),
PAGE = 0, ALIGN(4)
#endif
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/
