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Data receive/transmit clear. Use this bit to clear the data receive ready (DRRDY) bit and the data transmit ready (DXRDY) bit in the MMC status register 0 (MMCST0) before a new read or write sequence. This clears any previous status. 0 Do not clear DRRDY and DXRDY bits in MMCST0. 1 Clear DRRDY and DXRDY bits in MMCST0.
