TCRAM模块

谢谢您的答复。

这个问题已解决，可参考http://e2e.ti.com/support/microcontrollers/hercules/f/312/p/212035/757844.aspx

现在又有一个问题，下面代码中ramread = tcram1REG->RAMCTRL;和ramread = tcram2REG->RAMCTRL;这两步有何作用？为什么添加上以后debug不会发生double-bit错误？希望可以尽快答复，谢谢！！

void checkB0RAMECC(void)
{
 volatile uint32 ramread = 0U;
    volatile uint32 i;
/* USER CODE BEGIN (54) */
/* USER CODE END */

 /* enable writes to ECC RAM, enable ECC error response */
 tcram1REG->RAMCTRL = 0x0005010AU;   
 tcram2REG->RAMCTRL = 0x0005010AU;

 /* the first 1-bit error will cause an error response */
 tcram1REG->RAMTHRESHOLD = 0x1U;    
 tcram2REG->RAMTHRESHOLD = 0x1U;

 /* allow SERR to be reported to ESM */
 tcram1REG->RAMINTCTRL = 0x1U;    
 tcram2REG->RAMINTCTRL = 0x1U;
   
 /* cause a 1-bit ECC error */
 tcramA1bitError ^= 0x1U;
 
 /* disable writes to ECC RAM */
 tcram1REG->RAMCTRL = 0x0005000AU;   
 tcram2REG->RAMCTRL = 0x0005000AU;

 /* read from location with 1-bit ECC error */
 ramread = tcramA1bit;
 
 /* SERR not set in TCRAM1 or TCRAM2 modules */
 if ((!(((tcram1REG->RAMERRSTATUS & 1U) == 1U) || ((tcram2REG->RAMERRSTATUS & 1U) == 1U))) !=0U) 
 {
  /* TCRAM module does not reflect 1-bit error reported by CPU */
  tcramClass2Error();      
 }
 else
 {
     /* clear SERR flag */
  tcram1REG->RAMERRSTATUS = 0x1U;   
  tcram2REG->RAMERRSTATUS = 0x1U;
  
  /* clear status flags for ESM group1 channels 26 and 28 */
  esmREG->ESTATUS1[0U] = 0x14000000U;
  esmTriggerErrorPinReset();
 }

 /* enable writes to ECC RAM, enable ECC error response */
 tcram1REG->RAMCTRL = 0x0005010AU;   
 tcram2REG->RAMCTRL = 0x0005010AU;

 /* cause a 2-bit ECC error */
 tcramA2bitError ^= 0x3U;      
ramread = tcram1REG->RAMCTRL;

ramread = tcram2REG->RAMCTRL;

 /* read from location with 2-bit ECC error this will cause a data abort to be generated */
 ramread = tcramA2bit;

    /* delay before restoring the ram value */
 for(i=0U;i<10U;i++)
 {
 }

Hi yiwei,

不知道你用的Halcogen是哪个版本的。最新的03.06.00版本的Halcogen生成的sys_selftest.c中，checkB0RAMECC()函数中，没有这两句。这两句没有实际的意义。

void checkB0RAMECC(void)
{
    volatile uint32 ramread = 0U;
 uint64 tcramA1_bk = tcramA1bit;
 uint64 tcramA2_bk = tcramA2bit;
    uint32 i;
/* USER CODE BEGIN (36) */
/* USER CODE END */

    /* enable writes to ECC RAM, enable ECC error response */
    tcram1REG->RAMCTRL = 0x0005010AU;           
    tcram2REG->RAMCTRL = 0x0005010AU;

    /* the first 1-bit error will cause an error response */
    tcram1REG->RAMTHRESHOLD = 0x1U;               
    tcram2REG->RAMTHRESHOLD = 0x1U;

    /* allow SERR to be reported to ESM */
    tcram1REG->RAMINTCTRL = 0x1U;               
    tcram2REG->RAMINTCTRL = 0x1U;
   
    /* cause a 1-bit ECC error */
    tcramA1bitError ^= 0x1U;       
   
    /* disable writes to ECC RAM */
    tcram1REG->RAMCTRL = 0x0005000AU;           
    tcram2REG->RAMCTRL = 0x0005000AU;

    /* read from location with 1-bit ECC error */
    ramread = tcramA1bit;       
   
    /* SERR not set in TCRAM1 or TCRAM2 modules */
 /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */
 /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */
    if (!(((tcram1REG->RAMERRSTATUS & 1U) == 1U) || ((tcram2REG->RAMERRSTATUS & 1U) == 1U)))   
    {
        /* TCRAM module does not reflect 1-bit error reported by CPU */
        selftestFailNotification(CHECKB0RAMECC_FAIL1);
    }
    else
    {
        /* clear SERR flag */
        tcram1REG->RAMERRSTATUS = 0x1U;           
        tcram2REG->RAMERRSTATUS = 0x1U;
       
        /* clear status flags for ESM group1 channels 26 and 28 */
        esmREG->SR1[0U] = 0x14000000U;       
    }

    /* enable writes to ECC RAM, enable ECC error response */
    tcram1REG->RAMCTRL = 0x0005010AU;           
    tcram2REG->RAMCTRL = 0x0005010AU;

    /* cause a 2-bit ECC error */
    tcramA2bitError ^= 0x3U;

    /* read from location with 2-bit ECC error this will cause a data abort to be generated */
    ramread = tcramA2bit;

    /* delay before restoring the ram value */
    for(i=0U;i<10U;i++)
    {
    }/* Wait */           
   
    ramread = tcram1REG->RAMUERRADDR;
    ramread = tcram2REG->RAMUERRADDR;

    /* disable writes to ECC RAM */
    tcram1REG->RAMCTRL = 0x0005000AU;
    tcram2REG->RAMCTRL = 0x0005000AU;

    /* Compute correct ECC */
    tcramA1bit = tcramA1_bk;
    tcramA2bit = tcramA2_bk;                   
   
/* USER CODE BEGIN (37) */
/* USER CODE END */
}