For step changes at the input after start of conversion a settling time must be allowed before a valid conversion result is available. The SD16INTDLYx bits can provide sufficient filter settling time for a full-scale change at the ADC input.
SD16INTDLYx=0
如果我进行单次转换的时候，是不是每次启动的时候都要等到 第四次转换结束才会产生中断额
