msp4305529时钟例程改变ACLK的寄存器发现对smclk的值产生影响的原因

Haoji Wei 说：

在使用lunchpad用msp430F5529时，发现使用官方提供的时钟例程（见附件）时，用示波器观察smclk的波形，频率为8M，但是当把例程中第84行
UCSCTL4 |= SELA_2;                        // Set ACLK = REFO
注释掉后，（其余部分均不变）用示波器观察smclk的波形，smclk的频率变为了1.048M，是上电时的默认时钟频率，为什么改变ACLK的寄存器设置会影响smclk的值呢？

原因是这样的：

UCSCTL4 |= SELA_2;                        意思是 设置  ACLK = REFO

你把它注释掉了，那么，默认 就是 SELA_0， 意思是 ACLK = XT1. 也就是外部晶振。

然而你并没有在程序了配置并开启 XT1, 

所以程序跑到，

// Loop until XT1,XT2 & DCO stabilizes - In this case only DCO has to stabilize
do
{
UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG);
// Clear XT2,XT1,DCO fault flags
SFRIFG1 &= ~OFIFG; // Clear fault flags
}while (SFRIFG1&OFIFG); // Test oscillator fault flag

这里的时候， XT1LFOFFG 一直清不掉。程序也就一直卡在这里，输出的 SMCLK 也就是默认的 1.048MHz，因为还没有执行到后面的配置DCO语句

解决方案：

配置XT1

#include <msp430.h>

int main(void)
{
volatile unsigned int i;

WDTCTL = WDTPW+WDTHOLD; // Stop WDT
P1DIR |= BIT1; // P1.1 output

P1DIR |= BIT0; // ACLK set out to pins
P1SEL |= BIT0;
P2DIR |= BIT2; // SMCLK set out to pins
P2SEL |= BIT2;
P7DIR |= BIT7; // MCLK set out to pins
P7SEL |= BIT7;

UCSCTL3 = SELREF_2; // Set DCO FLL reference = REFO
// UCSCTL4 |= SELA_2; // Set ACLK = REFO

P5SEL |= BIT4+BIT5; // Select XT1
UCSCTL6 &= ~(XT1OFF); // XT1 On
UCSCTL6 |= XCAP_3; // Internal load cap

UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx

// Loop until XT1,XT2 & DCO stabilizes - In this case only DCO has to stabilize
do
{
UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG);
// Clear XT2,XT1,DCO fault flags
SFRIFG1 &= ~OFIFG; // Clear fault flags
}while (SFRIFG1&OFIFG); // Test oscillator fault flag

__bis_SR_register(SCG0); // Disable the FLL control loop
UCSCTL1 = DCORSEL_5; // Select DCO range 16MHz operation
UCSCTL2 |= 249; // Set DCO Multiplier for 8MHz
// (N + 1) * FLLRef = Fdco
// (249 + 1) * 32768 = 8MHz
__bic_SR_register(SCG0); // Enable the FLL control loop

// Worst-case settling time for the DCO when the DCO range bits have been
// changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx
// UG for optimization.
// 32 x 32 x 8 MHz / 32,768 Hz = 250000 = MCLK cycles for DCO to settle
__delay_cycles(250000);

while(1)
{
P1OUT ^= BIT1; // Toggle P1.1
__delay_cycles(600000); // Delay
}
}