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DMA出现bug 无法将数据传输到目的地址 而将数据传输到其他地址?????

Other Parts Discussed in Thread: MSP430F5529

#include "msp430f5529.h"

#include "HAL_PMM.h"

 

 //10K采样     

unsigned int voice_data[256];

volatile int DMAdone=0;

 

 

 

void main()

{

    WDTCTL = WDTPW + WDTHOLD;

    P6SEL |= BIT4;

    P5SEL |= BIT2+BIT3;                       //P5.2 P5.3 选择XT2晶振功能

    P5SEL |= BIT7;                            //P5.7设定为TB1定时器输

    P5DIR |= BIT7;                            //P5.7设为输出

    P2DIR |= BIT2;                             //SMCLK P2.2输出

    P2SEL |= BIT2;

    P7DIR |= BIT7;                             //MCLK P7.7输出

    P7SEL |= BIT7;

    P7SEL |= BIT6;                            //定时器输出

    P7DIR |= BIT6;

 

    UCSCTL6 &= ~(XT2OFF);

    SetVCore(3);

    __bis_SR_register(SCG0);

    UCSCTL0 = DCO1+DCO2+DCO3+DCO4;

    UCSCTL1 = DCORSEL_5;

    UCSCTL2 = FLLD_3 + 5;

    UCSCTL3 = SELREF_5 + FLLREFDIV_3;

    UCSCTL4 = SELA_4 + SELS_3 + SELM_3;

    UCSCTL5 = DIVA_5 + DIVS_1;

    __bic_SR_register(SCG0);

    __delay_cycles(8192);

    do

    {

         UCSCTL7 &= ~XT1LFOFFG;

    }while (UCSCTL7&XT1LFOFFG);

 

 

    ADC12CTL0 = ADC12ON;

    ADC12MCTL0 = ADC12INCH_4;

    ADC12IFG = 0;

    ADC12CTL0 |= ADC12SHT0_6;

    ADC12CTL1 = ADC12SHS_3 + ADC12CONSEQ_2 + ADC12CSTARTADD_0 + ADC12SHP + ADC12SSEL_2 + ADC12DIV_5;

    ADC12CTL0 |= ADC12ENC;

 

    TBCCR0 = 1200;

    TBCCR1 = 200;

    TBCCTL1 = OUTMOD_7;

    TBCTL = TBSSEL_2 + MC_1 + TBCLR + ID_0;

 

    DMACTL0 = DMA0TSEL_24;

    DMACTL4 = DMARMWDIS;

    DMA0CTL &= ~DMAIFG;

    DMA0CTL = DMADT_4+DMAEN+DMADSTINCR_3+DMAIE;

    DMA0SZ = 256;

 

    __data16_write_addr((unsigned short) &DMA0SA,(unsigned long) &ADC12MEM0);

    __data16_write_addr((unsigned short) &DMA0DA,(unsigned long) buffer);

    __bis_SR_register(GIE); //使能全局中断

    __delay_cycles(380000);

    while(1)

    {

        __delay_cycles(374400);

    }

}

 

 

 

 

#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)

#pragma vector=DMA_VECTOR

__interrupt void DMA_ISR(void)

#elif defined(__GNUC__)

void __attribute__ ((interrupt(DMA_VECTOR))) DMA_ISR (void)

#else

#error Compiler not supported!

#endif

{

  switch(__even_in_range(DMAIV,16))

  {

    case 0: break;

    case 2:     // DMA0IFG = DMA Channel 0

     //__delay_cycles(2048);

     if(DMAnum%2==1)

     {

     __no_operation();

        __data16_write_addr((unsigned short) &DMA0DA,(unsigned long) &buffer);       //更改地址

        __no_operation();

     }

     if(DMAnum%2==0)

        {

     __no_operation();

         __data16_write_addr((unsigned short) &DMA0DA,(unsigned long) &voice);  //更改地址

         __no_operation();

     }

    DMAnum=DMAnum+1;

       __no_operation();

      break;

    case 4: break;                          // DMA1IFG = DMA Channel 1

    case 6: break;                          // DMA2IFG = DMA Channel 2

    case 8: break;                          // DMA3IFG = DMA Channel 3

    case 10: break;                         // DMA4IFG = DMA Channel 4

    case 12: break;                         // DMA5IFG = DMA Channel 5

    case 14: break;                         // DMA6IFG = DMA Channel 6

    case 16: break;                         // DMA7IFG = DMA Channel 7

    default: break;

  }

}

数据经过DMA传输之后   会在两个数组存储  但是都说不是在正确的地址中    如果我配置的地址是   voice数组  就会传输到 buffer数组中    都是刚好相反的    

哪位可以告诉我一下为什么  谢谢

  • 建议参考下官网提供的例程

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    * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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    * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    *
    *******************************************************************************
    *
    * MSP430 CODE EXAMPLE DISCLAIMER
    *
    * MSP430 code examples are self-contained low-level programs that typically
    * demonstrate a single peripheral function or device feature in a highly
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    * register values and settings such as the clock configuration and care must
    * be taken when combining code from several examples to avoid potential side
    * effects. Also see www.ti.com/grace for a GUI- and www.ti.com/msp430ware
    * for an API functional library-approach to peripheral configuration.
    *
    * --/COPYRIGHT--*/
    //******************************************************************************
    // MSP430F552x Demo - DMA0, Single transfer using ADC12 triggered by TimerB
    //
    // Description: This software uses TBCCR1 as a sample and convert input into
    // the A0 of ADC12. ADC12IFG is used to trigger a DMA transfer and DMA
    // interrupt triggers when DMA transfer is done. TB1 is set as an output and
    // P1.0 is toggled when DMA ISR is serviced.
    // ACLK = REFO = 32kHz, MCLK = SMCLK = default DCO 1048576Hz
    //
    // MSP430F552x
    // -----------------
    // /|\| XIN|-
    // | | | 32kHz
    // --|RST XOUT|-
    // | |
    // | P1.0|-->LED
    // | P5.7|-->TB1 output
    // | |
    // | P6.0|<--A0
    //
    // Bhargavi Nisarga
    // Texas Instruments Inc.
    // April 2009
    // Built with CCSv4 and IAR Embedded Workbench Version: 4.21
    //******************************************************************************

    #include <msp430.h>

    unsigned int DMA_DST; // ADC conversion result is stored in this variable

    int main(void)
    {
    WDTCTL = WDTPW+WDTHOLD; // Hold WDT

    P1OUT &= ~BIT0; // P1.0 clear
    P1DIR |= BIT0; // P1.0 output
    P5SEL |= BIT7; // P5.7/TB1 option select
    P5DIR |= BIT7; // Output direction
    P6SEL |= BIT0; // Enable A/D channel A0

    //Setup Timer B0
    TBCCR0 = 0xFFFE;
    TBCCR1 = 0x8000;
    TBCCTL1 = OUTMOD_3; // CCR1 set/reset mode
    TBCTL = TBSSEL_2+MC_1+TBCLR; // SMCLK, Up-Mode

    // Setup ADC12
    ADC12CTL0 = ADC12SHT0_15+ADC12MSC+ADC12ON;// Sampling time, MSC, ADC12 on
    ADC12CTL1 = ADC12SHS_3+ADC12CONSEQ_2; // Use sampling timer; ADC12MEM0
    // Sample-and-hold source = CCI0B =
    // TBCCR1 output
    // Repeated-single-channel
    ADC12MCTL0 = ADC12SREF_0+ADC12INCH_0; // V+=AVcc V-=AVss, A0 channel
    ADC12CTL0 |= ADC12ENC;

    // Setup DMA0
    DMACTL0 = DMA0TSEL_24; // ADC12IFGx triggered
    DMACTL4 = DMARMWDIS; // Read-modify-write disable
    DMA0CTL &= ~DMAIFG;
    DMA0CTL = DMADT_4+DMAEN+DMADSTINCR_3+DMAIE; // Rpt single tranfer, inc dst, Int
    DMA0SZ = 1; // DMA0 size = 1

    __data16_write_addr((unsigned short) &DMA0SA,(unsigned long) &ADC12MEM0);
    // Source block address
    __data16_write_addr((unsigned short) &DMA0DA,(unsigned long) &DMA_DST);
    // Destination single address
    __bis_SR_register(LPM0_bits + GIE); // LPM0 w/ interrupts
    __no_operation(); // used for debugging
    }

    //------------------------------------------------------------------------------
    // DMA Interrupt Service Routine
    //------------------------------------------------------------------------------
    #if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
    #pragma vector=DMA_VECTOR
    __interrupt void DMA_ISR(void)
    #elif defined(__GNUC__)
    void __attribute__ ((interrupt(DMA_VECTOR))) DMA_ISR (void)
    #else
    #error Compiler not supported!
    #endif
    {
    switch(__even_in_range(DMAIV,16))
    {
    case 0: break;
    case 2: // DMA0IFG = DMA Channel 0
    P1OUT ^= BIT0; // Toggle P1.0 - PLACE BREAKPOINT HERE AND CHECK DMA_DST VARIABLE
    break;
    case 4: break; // DMA1IFG = DMA Channel 1
    case 6: break; // DMA2IFG = DMA Channel 2
    case 8: break; // DMA3IFG = DMA Channel 3
    case 10: break; // DMA4IFG = DMA Channel 4
    case 12: break; // DMA5IFG = DMA Channel 5
    case 14: break; // DMA6IFG = DMA Channel 6
    case 16: break; // DMA7IFG = DMA Channel 7
    default: break;
    }
    }