如图,当RX接收信号时,TX也有信号在输出,不知道为什么?
而从BULS1和BULS2之间输出的数据是正确的,可以读出来。
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如图,当RX接收信号时,TX也有信号在输出,不知道为什么?
而从BULS1和BULS2之间输出的数据是正确的,可以读出来。
波特率最低到300,TX和TX1还是有信号,应该不是RX、TX之间的串扰。我认为信号从BUSL上来的。如果把BUSL上的电压去掉,RX上输入信号,TX上就保持高电平和TX1保持低电平不变了。给RX输入信号时,BUSL1和BUSL2上的电压变化很小,基本没有变化啊?
W1是TVS管1SMA40CAT3G,下面是芯片上的说明:RX上有信号时,TX和TXI就是有信号,是RX的回显,芯片本来就是这样处理的吗
Because the TSS721A is configured for half-duplex only, the current modulation from RX or RXI is repeated
concurrently as ECHO on the outputs TX and TXI. If the slave, as well as the master, is trying to send
information via the lines, the added signals appear on the outputs TX and TXI, which indicates the data collision
to the slave