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如题，多谢……
USCI_A0, UART 9600 Full-Duplex Transceiver, 32K ACLK
int main(void)
{
WDTCTL = WDTPW+WDTHOLD; // Stop watchdog timer
P7SEL |= 0x03; // Port select XT1
do
UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG);
// Clear XT2,XT1,DCO fault flags
SFRIFG1 &= ~OFIFG; // Clear fault flags
__delay_cycles(100000); // Delay for Osc to stabilize
}while (SFRIFG1&OFIFG); // Test oscillator fault flag
P1OUT = 0x000; // P1.0/1 setup for LED output
P1DIR |= BIT0+BIT1; //
P3SEL |= BIT4+BIT5; // P3.4,5 UART option select
UCA0CTL1 |= UCSWRST; // **Put state machine in reset**
UCA0CTL1 |= UCSSEL_1; // CLK = ACLK
UCA0BR0 = 0x03; // 32k/9600 - 3.41
UCA0BR1 = 0x00; //
UCA0MCTL = 0x06; // Modulation
UCA0CTL1 &= ~UCSWRST; // **Initialize USCI state machine**
UCA0IE |= UCTXIE + UCRXIE; // Enable USCI_A0 TX/RX interrupt
}
希望能帮到你
请查看附件里的源代码；
根据自己的需求进行更改。
在CCS里面就带有源代码： C:\TI\ccsv5\ccs_base\msp430\msp430ware_1_10_02_21\examples\devices\5xx_6xx\MSP430F541xA, MSP430F543xA Code Examples\C
//****************************************************************************** // MSP430F543xA Demo - USCI_A0, 115200 UART Echo ISR, DCO SMCLK // // Description: Echo a received character, RX ISR used. Normal mode is LPM0. // USCI_A0 RX interrupt triggers TX Echo. // Baud rate divider with 1048576hz = 1048576/115200 = ~9.1 (009h|01h) // ACLK = REFO = ~32768Hz, MCLK = SMCLK = default DCO = 32 x ACLK = 1048576Hz // See User Guide for baud rate divider table // // MSP430F5438A // ----------------- // /|\| | // | | | // --|RST | // | | // | P3.4/UCA0TXD|------------> // | | 115200 - 8N1 // | P3.5/UCA0RXD|<------------ // // M. Morales // Texas Instruments Inc. // June 2009 // Built with CCE Version: 3.2.2 and IAR Embedded Workbench Version: 4.11B //****************************************************************************** #include "msp430x54xA.h" void main(void) { WDTCTL = WDTPW + WDTHOLD; // Stop WDT P3SEL = 0x30; // P3.4,5 = USCI_A0 TXD/RXD UCA0CTL1 |= UCSWRST; // **Put state machine in reset** UCA0CTL1 |= UCSSEL_2; // SMCLK UCA0BR0 = 9; // 1MHz 115200 (see User's Guide) UCA0BR1 = 0; // 1MHz 115200 UCA0MCTL |= UCBRS_1 + UCBRF_0; // Modulation UCBRSx=1, UCBRFx=0 UCA0CTL1 &= ~UCSWRST; // **Initialize USCI state machine** UCA0IE |= UCRXIE; // Enable USCI_A0 RX interrupt __bis_SR_register(LPM0_bits + GIE); // Enter LPM0, interrupts enabled __no_operation(); // For debugger } // Echo back RXed character, confirm TX buffer is ready first #pragma vector=USCI_A0_VECTOR __interrupt void USCI_A0_ISR(void) { switch(__even_in_range(UCA0IV,4)) { case 0:break; // Vector 0 - no interrupt case 2: // Vector 2 - RXIFG while (!(UCA0IFG&UCTXIFG)); // USCI_A0 TX buffer ready? UCA0TXBUF = UCA0RXBUF; // TX -> RXed character break; case 4:break; // Vector 4 - TXIFG default: break; } }
