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void vPortsd24Stop()
{
SD24INCTL2 &= ~SD24SC; // Set bit to start conversion
sd24OK = TRUE;
}
BOOL xPortsd24Init( UCHAR delay,UCHAR num)
{
BOOL bInitialized = TRUE;
sd24num = num;
// Configure GPIO
SD24CTL = SD24REFS; // Internal ref
SD24CCTL0 |= SD24GRP | SD24DF | SD24IFG | SD24SNGL; // Enable interrupt
SD24INCTL0 |= SD24INCH_6;
SD24CCTL1 |= SD24GRP | SD24DF | SD24IFG;
SD24CCTL2 |= SD24IE | SD24DF | SD24IFG;
SD24INCTL1 |= SD24GAIN_16;
SD24INCTL2 |= SD24GAIN_16;
SD24PRE1 = delay;
SD24PRE2 = delay;
delay_us(10);
return bInitialized;
}
在使用过程中,一块完整的片子,扫入代码,启动SD24后,一直进入low_level_init文件中system_pre_init中,
完整片子时钟测试输出是1.648M,运行程序后,通过IO输出时钟22.5M.使用的是smlck。
如下是sd24初始化和使用的low_level_init文件
BOOL xPortsd24Init( UCHAR delay,UCHAR num)
{
BOOL bInitialized = TRUE;
sd24num = num;
// Configure GPIO
SD24CTL = SD24REFS; // Internal ref
SD24CCTL0 |= SD24GRP | SD24DF | SD24IFG | SD24SNGL; // Enable interrupt
SD24INCTL0 |= SD24INCH_6;
SD24CCTL1 |= SD24GRP | SD24DF | SD24IFG;
SD24CCTL2 |= SD24IE | SD24DF | SD24IFG;
SD24INCTL1 |= SD24GAIN_16;
SD24INCTL2 |= SD24GAIN_16;
SD24PRE1 = delay;
SD24PRE2 = delay;
/*SD24_init(SD24_BASE, SD24_REF_INTERNAL); // Select internal REF
SD24_initConverterAdvancedParam param = {0};
param. converter = SD24_CONVERTER_2; // Select converter
param. conversionMode = SD24_SINGLE_MODE; // Select single mode
param. groupEnable = SD24_NOT_GROUPED; // No grouped
param. inputChannel = SD24_INPUT_CH_ANALOG; // Input from analog signal
param. dataFormat = SD24_DATA_FORMAT_2COMPLEMENT; // 2鈥檚 complement data format
param. interruptDelay = SD24_FOURTH_SAMPLE_INTERRUPT; // 4th sample causes interrupt
param. oversampleRatio = SD24_OVERSAMPLE_256; // Oversampling ratio 256
param. gain = SD24_GAIN_1; // Preamplifier gain x1
SD24_initConverterAdvanced(SD24_BASE, 露m);
delay cycles(0x3600); // Delay for 1.5V REF startup*/
delay_us(10);
return bInitialized;
}
#ifdef __TI_COMPILER_VERSION__
int _system_pre_init(void)
#elif __IAR_SYSTEMS_ICC__
int __low_level_init(void)
#elif __GNUC__
extern int system_pre_init(void) __attribute__((constructor));
int system_pre_init(void)
#else
#error Compiler not supported!
#endif
{
unsigned long *jtagPwd = (unsigned long *)JTAG_DIS_PWD1;
/* Feed the watchdog timer */
WDTCTL = WDTPW | WDTCNTCL;
/* Check JTAG password locations and disable JTAG if passwords don't match.
* Else the JTAG will be enabled in the 64th cycle after reset.
*/
if ((*jtagPwd != 0x00000000) && (*jtagPwd != 0xFFFFFFFF))
{
/* Disable JTAG */
SYSJTAGDIS = JTAGDISKEY;
}
/* Calibration section
* Check for the BORIFG flag in IFG1. Execute calibration if this was a BORIFG.
* Else skip calibration
*/
if (IFG1 & BORIFG)
{
/* Perform 2's complement checksum on 62 bytes of TLV data */
unsigned int checksum = 0;
unsigned char *TLV_address_for_parse = ((unsigned char *)TLV_START);
unsigned int *TLV_address_for_checksum = ((unsigned int *)TLV_START + 1);
do
{
checksum ^= *TLV_address_for_checksum++;
} while (TLV_address_for_checksum <= (unsigned int *)TLV_END);
checksum ^= 0xFFFF;
checksum++;
/* If check sum is not correct go to LPM4 */
if (*((unsigned int *)TLV_START) != checksum)
{
/* Enter LPM4 if checksum failed */
__bis_SR_register(LPM4_bits);
}
/* Check sum matched, now set calibration values */
/* Calibrate REF */
REFCAL1 = *(TLV_address_for_parse + TLV_CAL_REFCAL1);
REFCAL0 = *(TLV_address_for_parse + TLV_CAL_REFCAL0);
/* Calibrate DCO */
CSIRFCAL = *(TLV_address_for_parse + TLV_CAL_CSIRFCAL);
CSIRTCAL = *(TLV_address_for_parse + TLV_CAL_CSIRTCAL);
CSERFCAL = *(TLV_address_for_parse + TLV_CAL_CSERFCAL);
CSERTCAL = *(TLV_address_for_parse + TLV_CAL_CSERTCAL);
/* Calibrate SD24 */
SD24TRIM = *(TLV_address_for_parse + TLV_CAL_SD24TRIM);
/* Clear BORIFG */
IFG1 &= ~(BORIFG);
}
/* Feed the watchdog timer */
WDTCTL = WDTPW | WDTCNTCL;
/* Return value:
* 1 - Perform data segment initialization.
* 0 - Skip data segment initialization.
*/
return 1;
}