极低功耗.设置： ACLK = VL0, MCLK = VLO/8 ~1.5kHz, SMCLK = 无

贴一下该程序的详细说明，请您参考一下

#include <msp430g2553.h>

//This small set of code takes care of an inconsistency between g2553 and g2231. It should be present.

#ifndef TIMER0_A1_VECTOR
#define TIMER0_A1_VECTOR TIMERA1_VECTOR
#define TIMER0_A0_VECTOR TIMERA0_VECTOR
#endif

void main(void)
{
 //code goes here
 
WDTCTL = WDTPW + WDTHOLD;  //disables the watchdog timer by sending the  password (WDTPW) and hold command (WDTHOLD) 
 
P1DIR = 0x40;    //making the port pin 6 as output
P1OUT = 0;        // initializing the port pin to zero
 
BCSCTL3 |= LFXT1S_2; //Type 1: Operate Master clock on VLOCLK. BCSCTL3 has a default condition of 5 (in decimal) which corresponds to certain settings. Look at user manual for these settings. Now ORing with LFXT1S_2 (which is 0x20 defined as per header file), will result if 37 (in decimal) which leads to selection (refer user guide) of VLO (low frequency clock) and other settings. For more details visit Chapter 5 of User Guide.

//MCLK is set to use DCO in case of a fault by default

IFG1 &= ~OFIFG; //we are clearing this default flag. (IFG1: interrupt flag register 1) This step clears bit 1 (bit naming starts from 0). (OFIFG: oscillator fault interrupt flag register)

_bis_SR_register(SCG1 + SCG0);  //We need to wait for 50us for the clock system to respond to this change (see 5.2.7.1 in user guide). This can be accomplished by executing one instruction for a 12KHz VLOCLK. This disables system clock generators in the register. The underscore before the statement defines this statement as an Assembly level call from C. Its a Bit Set Operation. Its a Bit Set Operation. SCG1 when set turns off the SMCLK. When SCG0 is set it turns off DCO. This probably helps to save power.

BCSCTL2 |= SELM_3 + DIVM_3; //It is used to source the master clock from VLOCLK. This is accomplished by setting bit 6,7 as 11. SELM_3 is a binary number (1100 0000) which does the job. In order to divide the clock by 8, bits 4,5 should be set as 11. This is accomplished by adding DIVM_3 (00 11 00 00) to SELM_3.

//This completes the clock configuration step. Now the infinite loop can be coded to execute a simple task, like toggling LED, forever. The use of delay function in this block will generate a delay before and after toggle. The delay function takes in no. of clock cycles as a parameter. So this delay is dependent on the clock frequency.

while(1)
{
  P1OUT = 0x40;                            // LED on
  _delay_cycles(100);
  P1OUT = 0;                                 // LED off
  _delay_cycles(5000);
}

#include <msp430g2553.h>

//This small set of code takes care of an inconsistency between g2553 and g2231. It should be present.

#ifndef TIMER0_A1_VECTOR
#define TIMER0_A1_VECTOR TIMERA1_VECTOR
#define TIMER0_A0_VECTOR TIMERA0_VECTOR
#endif

void main(void)
{
//code goes here

WDTCTL = WDTPW + WDTHOLD;  //disables the watchdog timer by sending the  password (WDTPW) and hold command (WDTHOLD)

P1DIR = 0x40;    //making the port pin 6 as output
P1OUT = 0;        // initializing the port pin to zero

BCSCTL3 |= LFXT1S_2; //Type 1: Operate Master clock on VLOCLK. BCSCTL3 has a default condition of 5 (in decimal) which corresponds to certain settings. Look at user manual for these settings. Now ORing with LFXT1S_2 (which is 0x20 defined as per header file), will result if 37 (in decimal) which leads to selection (refer user guide) of VLO (low frequency clock) and other settings. For more details visit Chapter 5 of User Guide.

//MCLK is set to use DCO in case of a fault by default

IFG1 &= ~OFIFG; //we are clearing this default flag. (IFG1: interrupt flag register 1) This step clears bit 1 (bit naming starts from 0). (OFIFG: oscillator fault interrupt flag register)

_bis_SR_register(SCG1 + SCG0);  //We need to wait for 50us for the clock system to respond to this change (see 5.2.7.1 in user guide). This can be accomplished by executing one instruction for a 12KHz VLOCLK. This disables system clock generators in the register. The underscore before the statement defines this statement as an Assembly level call from C. Its a Bit Set Operation. Its a Bit Set Operation. SCG1 when set turns off the SMCLK. When SCG0 is set it turns off DCO. This probably helps to save power.

BCSCTL2 |= SELM_3 + DIVM_3; //It is used to source the master clock from VLOCLK. This is accomplished by setting bit 6,7 as 11. SELM_3 is a binary number (1100 0000) which does the job. In order to divide the clock by 8, bits 4,5 should be set as 11. This is accomplished by adding DIVM_3 (00 11 00 00) to SELM_3.

//This completes the clock configuration step. Now the infinite loop can be coded to execute a simple task, like toggling LED, forever. The use of delay function in this block will generate a delay before and after toggle. The delay function takes in no. of clock cycles as a parameter. So this delay is dependent on the clock frequency.

while(1)
{
 P1OUT = 0x40;                            // LED on
 _delay_cycles(100);
 P1OUT = 0;                                 // LED off
 _delay_cycles(5000);
}