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MSP430F4152 DCO倍频到8MHZ的例程有没有

SCFI0 |= FN_4;                            // x2 DCO freq, 8MHz nominal DCO

SCFQCTL = 121;                            // (121+1) x 32768 x 2 = 7.99 Mhz

FLL_CTL0 |= DCOPLUS + XCAP11PF;           // DCO+ set so freq= xtal x D x N+1

官方给的例程测试有问题,有时候会失败。

  • 请问能给出完整程序或者程序出处吗?另外您现在使用的是自己制作的板子?

    例程的话,您可以参考下面的代码

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     *                       MSP430 CODE EXAMPLE DISCLAIMER
     *
     * MSP430 code examples are self-contained low-level programs that typically
     * demonstrate a single peripheral function or device feature in a highly
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     * for an API functional library-approach to peripheral configuration.
     *
     * --/COPYRIGHT--*/
    //******************************************************************************
    //  MSP430x41x2 Demo - FLL+, Runs Internal DCO at 8 MHz
    //
    //  Description: This program demonstrates setting the internal DCO to run at
    //  8MHz with auto-calibration by the FLL+ circuitry.
    //  ACLK = LFXT1 = 32768Hz, MCLK = SMCLK = DCO = (121+1) x 32768 x 2 = 7.99 Mhz
    //  //* An external watch crystal between XIN & XOUT is required for ACLK *//	
    //
    //                 MSP430x41x2
    //             -----------------
    //         /|\|              XIN|-
    //          | |                 | 32kHz
    //          --|RST          XOUT|-
    //            |                 |
    //            |             P1.1|--> MCLK = 8MHz
    //            |                 |
    //            |             P1.6|--> ACLK = 32.768kHz
    //            |                 |
    //
    //  P. Thanigai
    //  Texas Instruments Inc.
    //  January 2009
    //  Built with CCE Version: 3.1 and IAR Embedded Workbench Version: 4.11
    //*****************************************************************************
    #include <msp430.h>
    
    int main(void)
    {
      WDTCTL = WDTPW + WDTHOLD;                 // Stop watchdog timer
      SCFI0 |= FN_4;                            // x2 DCO freq, 8MHz nominal DCO
      SCFQCTL = 121;                            // (121+1) x 32768 x 2 = 7.99 Mhz
      FLL_CTL0 |= DCOPLUS + XCAP11PF;           // DCO+ set so freq= xtal x D x N+1
    
      P1DIR = BIT1+BIT6;                        // P1.1 & P1.6 to output direction
      P1SEL = BIT1+BIT6;                        // P1.1 & P1.6 to output MCLK & ACLK
    
      while(1);                                 // Loop in place
    }
    
    

  • 这个例程测试了,有时候上电出来的频率不对,不开启DCOPLUS 都是对的。。。不知道开启DCOPLUS是不是有什么注意事项。。。
  • 关于DCOPLUS,有如下描述

    The DCOPLUS bit sets the fDCOCLK frequency to fDCO or fDCO/D. The FLLDx bits configure the divider, D, to 1, 2, 4, or 8. By default, DCOPLUS = 0 and D = 2, providing a clock frequency of fDCO/2 on fDCOCLK.

    The multiplier (N+1) and D set the frequency of DCOCLK.

    DCOPLUS = 0: fDCOCLK = (N + 1) x fACLK
    DCOPLUS = 1: fDCOCLK = D x (N + 1) x fACLK

    在代码中使用的是

    #define XCAP11PF (0x30) /* XIN Cap = XOUT Cap = 11pf */

    您现在使用的电容是多大?