关于MSP430F5438a PWM输出用了TA1.0对应引脚，是不是只能调整周期，不能调整占空比？

楼主你好！

每一种模式都可以输出占空比可调的方波。而且能且仅能产生方波。楼主可以参考下面代码：

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//*******************************************************************************
// MSP430F543xA Demo - Timer_A3, PWM TA1.1-2, Up/Down Mode, DCO SMCLK
//
// Description: This program generates two PWM outputs on P2.2,3 using
// Timer1_A configured for up/down mode. The value in CCR0, 128, defines the
// PWM period/2 and the values in CCR1 and CCR2 the PWM duty cycles. Using
// ~1.045MHz SMCLK as TACLK, the timer period is ~233us with a 75% duty cycle
// on P2.2 and 25% on P2.3.
// SMCLK = MCLK = TACLK = default DCO ~1.045MHz.
//
// MSP430F5438A
// -------------------
// /|\| |
// | | |
// --|RST |
// | |
// | P2.2/TA1.1|--> CCR1 - 75% PWM
// | P2.3/TA1.2|--> CCR2 - 25% PWM
//
// M. Morales
// Texas Instruments Inc.
// June 2009
// Built with CCE Version: 3.2.2 and IAR Embedded Workbench Version: 4.11B
//******************************************************************************

#include <msp430.h>

int main(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
P2DIR |= 0x0C; // P2.2 and P2.3 output
P2SEL |= 0x0C; // P2.2 and P2.3 options select
TA1CCR0 = 128; // PWM Period/2
TA1CCTL1 = OUTMOD_6; // CCR1 toggle/set
TA1CCR1 = 32; // CCR1 PWM duty cycle
TA1CCTL2 = OUTMOD_6; // CCR2 toggle/set
TA1CCR2 = 96; // CCR2 PWM duty cycle
TA1CTL = TASSEL_2 + MC_3 + TACLR; // SMCLK, up-down mode, clear TAR

__bis_SR_register(LPM0_bits); // Enter LPM0
__no_operation(); // For debugger
}

Billy 你好！

你给我的例程我也有，我的旧版本设备硬件就是用TA1.1对应引脚P8.6。但是我输出的是TA1.0的相应引脚，不知你们有否试过输出TA1.0或者或者TA1.0的相应引脚，

我上网查基本都是TAx.1和TAx.2的用法，就没见过有人用输出TA1.0或者或者TA1.0的相应引脚。

还是原来的问题，我用io口P8.5输出可调占空比的PWM，怎么输出？

Xutong Han2 你好

根据我的调试，就是你所说的那样，谢谢你，这样我好去跟我做硬件的同时说清楚让他改硬件。。

我试过你所说的方法，但是不行，无论是continuous还是其他模式，用MODE4。。

CCR0控制周期/频率，CCR1控制占空比。在CCR0中断中GPIO = 0；CCR1中断中GPIO = 1；upmode、downmode、updownmode都可以。