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MSP430FR2476: 定时器使用问题

Part Number: MSP430FR2476
问题现象
1.timer_a当作定时器使用,timer_b用来产生pwm,在两者同时使用时,timer_b就无法产生pwm波形。
2.单独跑timer_b的pwm就是正常的
还请协助看下是哪里的问题导致,谢谢!
我这边配置代码如下:
    P4DIR |= BIT7;// P4.7 output
    P4SEL1 |= BIT7;// P4.7 options select, TB0.1
    P5DIR |= BIT0;// P5.0 output
    P5SEL1 |= BIT0;// P5.0 options select, TB0.2
    // Disable the GPIO power-on default high-impedance mode to activate
    // previously configured port settings
    PM5CTL0 &= ~LOCKLPM5;

    TB0CCR0 = 128;// PWM Period/2
    TB0CCTL1 = OUTMOD_2 |CLLD_2;// TBCCR1 toggle/reset; CLLD=2
    TB0CCR1 = 32;// TBCCR1 PWM duty cycle
    TB0CCTL2 = OUTMOD_6 | CLLD_2;              // TBCCR2 toggle/set; CLLD=2
    TB0CCR2 = 64;// TBCCR2 PWM duty cycle
    TB0CTL = TBSSEL__ACLK | MC_3 | TBCLGRP_1;// ACLK, up-down mode, TBxCL1+TBxCL2 group

    TA0CCTL0 |= CCIE;// TACCR0 interrupt enabled
    TA0CCR0 = 50000;
    TA0CTL |= TASSEL__SMCLK | MC__UP;// SMCLK, up mode
  • 您好,您是基于哪个例程做的修改?

  • 您好,是技术支持那边提供的这个MSP430FR267x_MSP430FR247x_Code_Examples。

    1.timer_a使用MSP430FR267x_MSP430FR247x_Code_Examples\C\msp430fr267x_TA0_01.c的示例代码;
    2.timer_b使用MSP430FR267x_MSP430FR247x_Code_Examples\C\msp430fr267x_TB0_shadow_register.c的示例代码。
  • 我这里没有问题,附上我的代码:

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     *                       MSP430 CODE EXAMPLE DISCLAIMER
     *
     * MSP430 code examples are self-contained low-level programs that typically
     * demonstrate a single peripheral function or device feature in a highly
     * concise manner. For this the code may rely on the device's power-on default
     * register values and settings such as the clock configuration and care must
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     * for an API functional library-approach to peripheral configuration.
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    //******************************************************************************
    //  MSP430FR267x Demo - Timer0_B7, PWM TB0.1-2, Up/Down Mode, 32kHz ACLK.
    //                      Showcase double-buffered TBxCCRn feature.
    //
    //  Description: This program generates two PWM outputs on P4.7, P5.0 using
    //  Timer_B configured for up/down mode. Timer_B TBxCCRn registers are
    //  double-buffered and can be grouped. In this program, TB0CCR1 and TB0CCR2
    //  are grouped and loaded to shadow registers(TB0CL1&TB0CL2) simultaneously.
    //  Normal operating mode is LPM3.
    //  ACLK = TBCLK = REFO = 32768Hz, MCLK = 1MHz(default)
    //                MSP430FR2676
    //         ---------------
    //     /|\|               |
    //      | |               |
    //      --|RST            |
    //        |     P4.7/TB0.1|-->
    //        |               |
    //        |     P5.0/TB0.2|-->
    //
    //**********************************************************
    //
    //  MSP430FR267x Demo - Timer0_A3, Toggle P1.0, CCR0 Count Mode ISR, DCO SMCLK
    //
    //  Description: Toggle P1.0 using software and TA_0 ISR. Timer0_A is
    //  configured for continuous mode, thus the timer overflows when TAR counts
    //  to CCR0. In this example, CCR0 is loaded with 50000.
    //  ACLK = n/a, MCLK = SMCLK = TACLK = default DCO = ~1MHz
    //
    //                MSP430FR2676
    //             -----------------
    //         /|\|                 |
    //          | |                 |
    //          --|RST              |
    //            |                 |
    //            |             P1.0|--> LED
    //
    //**********************************************************
    //combined above two demos
    //**********************************************************
    //
    //   Longyu Fang
    //   Texas Instruments Inc.
    //   August 2018
    //   Built with IAR Embedded Workbench v7.12.1 & Code Composer Studio v8.1.0
    //******************************************************************************
    #include <msp430.h>
    
    int main(void)
    {
        WDTCTL = WDTPW | WDTHOLD;                  // Stop WDT
        P4DIR |= BIT7;                      // P4.7 output
        P4SEL1 |= BIT7;                     // P4.7 options select, TB0.1
        P5DIR |= BIT0;                      // P5.0 output
        P5SEL1 |= BIT0;                     // P5.0 options select, TB0.2
    
        P1DIR |= BIT0;                                // P1.0 output
        P1OUT |= BIT0;                                // P1.0 high
    
        // Disable the GPIO power-on default high-impedance mode to activate
        // previously configured port settings
        PM5CTL0 &= ~LOCKLPM5;
    
        TB0CCR0 = 128;                             // PWM Period/2
        TB0CCTL1 = OUTMOD_2 |CLLD_2;               // TBCCR1 toggle/reset; CLLD=2
        TB0CCR1 = 32;                              // TBCCR1 PWM duty cycle
        TB0CCTL2 = OUTMOD_6 | CLLD_2;              // TBCCR2 toggle/set; CLLD=2
        TB0CCR2 = 64;                              // TBCCR2 PWM duty cycle
    
    
        TA0CCTL0 |= CCIE;                             // TACCR0 interrupt enabled
        TA0CCR0 = 50000;
    
        TB0CTL = TBSSEL__ACLK | MC_3 | TBCLGRP_1;  // ACLK, up-down mode, TBxCL1+TBxCL2 group
        TA0CTL |= TASSEL__SMCLK | MC__CONTINUOUS;     // SMCLK, continuous mode
    
    
        __bis_SR_register(LPM0_bits | GIE);           // Enter LPM0 w/ interrupts
        __no_operation();                             // For debug
    
    }
    
    // Timer A0 interrupt service routine
    #if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
    #pragma vector = TIMER0_A0_VECTOR
    __interrupt void Timer_A (void)
    #elif defined(__GNUC__)
    void __attribute__ ((interrupt(TIMER0_A0_VECTOR))) Timer_A (void)
    #else
    #error Compiler not supported!
    #endif
    {
        P1OUT ^= BIT0;
        TA0CCR0 = 50000;                             // Add Offset to TACCR0
    }