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msp430的24位AD使用问题

Other Parts Discussed in Thread: MSP430AFE253, MSP430F4270

1、我用到高精度24位AD,我主要参考官方例程,发现MSP430F4270的例程中有过采样率1024的,但是只读出低十六位。我想用msp430afe253读出24位AD数应该怎么改造。
请把下面代码改造成msp430afe253的24位精度的例程。

2、下图是430指南的截图,我的问题是两次读取,重叠的部分怎么处理?

代码如下
MSP430F4270
//             -----------------
//         /|\|              XIN|-
//          | |                 | 32kHz
//          --|RST          XOUT|-
//            |                 |
//    Vin+ -->|A0+              |
//    Vin- -->|A0-              |
//            |                 |
//            |            VREF |---+
//            |                 |   |
//            |                 |  -+- 100nF
//            |                 |  -+-
//            |                 |   |
//            |            AVss |---+
//            |                 |
//
//  L. Westlund / S. Karthikeyan
//  Texas Instruments Inc.
//  June 2005
//  Built with CCE Version: 3.2.0 and IAR Embedded Workbench Version: 3.30A
//*****************************************************************************
#include <msp430.h>

unsigned int result;

int main(void)
{
  volatile unsigned int i;                  // Use volatile to prevent removal
                                            // by compiler optimization

  WDTCTL = WDTPW + WDTHOLD;                 // Stop WDT
  FLL_CTL0 |= XCAP14PF;                     // Configure load caps
  for (i = 0; i < 10000; i++);              // Delay for 32 kHz crystal to
                                            // stabilize

  SD16CTL = SD16REFON+SD16SSEL0;            // 1.2V ref, SMCLK
  SD16CCTL0 |= SD16SNGL+SD16IE+SD16XOSR+SD16OSR0;// Single conv, enable interrupt, 1024 OSR
  SD16INCTL0 |= SD16INTDLY_0;               // Interrupt on 4th sample
  for (i = 0; i < 0x3600; i++);             // Delay for 1.2V ref startup

  _EINT();                                  // Enable general interrupts

  while (1)
  {
    SD16CCTL0 |= SD16SC;                    // SET BREAKPOINT HERE
                                            // Set bit to start conversion
    _BIS_SR(LPM0_bits);                     // Enter LPM0
  }
}

#pragma vector=SD16_VECTOR
__interrupt void SD16ISR(void)
{
  switch (SD16IV)
  {
  case 2:                                   // SD16MEM Overflow
    break;
  case 4:                                   // SD16MEM0 IFG
    result = SD16MEM0;                      // Save CH0 results (clears IFG)
    break;
  }

  _BIC_SR_IRQ(LPM0_bits);                   // Exit LPM0
}

  • 1.AFE253自带24位Sigma Delta ADC,而F4270为16位SD,我想可以直接使用24位AD。

    例程:http://www.ti.com/lit/zip/slac487

    范例:

    //*****************************************************************************
    // MSP430AFE25x Demo - SD24, Continuous Conversion on a Group of 3 Channels
    //
    // Description: This program uses the SD24 module to perform continuous
    // conversions on a group of channels (0, 1 and 2). A SD24 interrupt occurs
    // whenever the conversions have completed. Test by applying voltages to the
    // 3 input channels and setting a breakpoint at the line indicated
    // below. Run program until it reaches the breakpoint, then use
    // the debugger's watch window to view the conversion results. Results
    // (upper 16 bits only) are stored in three arrays, one for each channel.
    // ACLK = n/a, MCLK = SMCLK = DCO = ~ 1.1MHz
    // //* For minimum Vcc required for SD24 module - see datasheet *//
    // //* 100nF cap btw Vref and AVss is recommended when using 1.2V ref *//
    //
    // MSP430AFE25x
    // -----------------
    // /|\| XIN|-
    // | | |
    // --|RST XOUT|-
    // | |
    // Vin1+ -->|A0.0+ |
    // Vin1- -->|A0.0- |
    // Vin2+ -->|A1.0+ |
    // Vin2- -->|A1.0- |
    // Vin3+ -->|A2.0+ |
    // Vin3- -->|A2.0- |
    // | VREF |---+
    // | | |
    // | | -+- 100nF
    // | | -+-
    // | | |
    // | AVss |---+
    // | |
    //
    // Naveen Kala
    // Texas Instruments, Inc
    // March 2011
    // Built with IAR Embedded Workbench Version: 5.20.1
    //*****************************************************************************
    #include <msp430afe253.h>

    #define Num_of_Results 8

    /* Arrays to store SD24 conversion results */
    unsigned int Ch0results[Num_of_Results];
    unsigned int Ch1results[Num_of_Results];
    unsigned int Ch2results[Num_of_Results];

    void main(void)
    {
    volatile unsigned int i; // Use volatile to prevent removal
    // by compiler optimization

    WDTCTL = WDTPW + WDTHOLD; // Stop WDT

    P1DIR |= BIT0+BIT1; // Set P1.0, P1.1 to output
    SD24CTL = SD24REFON + SD24SSEL0; // 1.2V ref, SMCLK
    SD24CCTL0 |= SD24GRP+SD24DF; // Group with CH1
    SD24CCTL1 |= SD24GRP+SD24DF; // Group with CH2
    SD24CCTL2 |= SD24IE+SD24DF; // Enable interrupt
    for (i = 0; i < 0x3600; i++); // Delay for 1.2V ref startup

    SD24CCTL2 |= SD24SC; // Set bit to start conversion
    __bis_SR_register(LPM0_bits + GIE); // Enter LPM0 w/ interrupts
    }

    #pragma vector=SD24_VECTOR
    __interrupt void SD24AISR(void)
    {
    static unsigned int index = 0;

    switch (SD24IV)
    {
    case 2: // SD24MEM Overflow
    break;
    case 4: // SD24MEM0 IFG
    break;
    case 6: // SD24MEM1 IFG
    break;
    case 8: // SD24MEM2 IFG
    Ch0results[index] = SD24MEM0; // Save CH0 results (clears IFG)
    Ch1results[index] = SD24MEM1; // Save CH1 results (clears IFG)
    Ch2results[index] = SD24MEM2; // Save CH2 results (clears IFG)
    P1OUT ^=BIT0;
    if (++index == Num_of_Results)
    {
    index = 0; // SET BREAKPOINT HERE
    P1OUT ^=BIT1;
    }
    break;
    }
    }