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SPI通信过程中,采用官网两个单片机相互通信,数据累加发送接收的程序中,发送正常。接受数据容易发生跳变。应考虑是什么因素影响?
另外,参考5529的接收子程序,其中有x=UCB0RXBUF;而在6659的应用中,x无法读取UCB0RXBUF中的数据,应该怎么处理呢?
主机程序如下:
// MSP430F534x
// -----------------
// /|\| |
/ | | |
// --| RST P5.6|-> LED
// | |
// | | P2.2|-> Master Data Out (UCB0SIMO)
// | | | |
// | P2.3|<- Master Data In (UCB0SOMI)
// | |
// Slave reset <-|P2.6
P2.1|-> Serial Clock Out (UCB0CLK)
//
//
// Bhargavi Nisarga
// Texas Instruments Inc.
// Jun 2011
// Built with CCSv4 and IAR Embedded Workbench Version: 4.21
//******************************************************************************
#include <msp430.h>
#define SPI_CLK BIT1
#define SPI_SIMO BIT2
#define SPI_SOMI BIT3
#define SPI_STE BIT6
// Ports
#define SPI_SEL P2SEL
#define SPI_DIR P2DIR
#define SPI_OUT P2OUT
#define SPI_REN P2REN
unsigned char MST_Data,SLV_Data;
unsigned char temp;
int main(void)
{
volatile unsigned int i;
WDTCTL = WDTPW+WDTHOLD; // Stop watchdog timer
P5OUT |= BIT6; // Set P5.6 for LED
// Set P1.1 for slave reset
P5DIR |= BIT6; // Set P1.0-2 to output direction
P2OUT |= BIT6;
P2SEL |= BIT1+BIT2+BIT3; // P3.3,4 option select
P2DIR |= BIT6; //P2.7 RST
UCB0CTL1 |= UCSWRST; // **Put state machine in reset**
UCB0CTL0 |= UCMST+UCSYNC+UCMSB+UCCKPL; // 3-pin, 8-bit SPI master
UCB0CTL1 |= UCSSEL_2; // SMCLK
UCB0BR0 = 0x02; // /2
UCB0BR1 = 0; //
// UCB0MCTL = 0; // No modulation
UCB0CTL1 &= ~UCSWRST; // **Initialize USCI state machine**
UCB0IE |= UCRXIE; // Enable USCI_A0 RX interrupt
P2OUT &=~ BIT6; // Now with SPI signals initialized,
P2OUT |= BIT6;
// reset slave
for(i=50;i>0;i--); // Wait for slave to initialize
MST_Data = 0x01; // Initialize data values
SLV_Data = 0x00;
while (!(UCB0IFG&UCTXIFG)); // USCI_A0 TX buffer ready?
UCB0TXBUF = MST_Data;
__bis_SR_register(LPM0_bits + GIE); // CPU off, enable interrupts
}
#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector=USCI_B0_VECTOR
__interrupt void USCI_B0_ISR(void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(USCI_B0_VECTOR))) USCI_B0_ISR (void)
#else
#error Compiler not supported!
#endif
{
volatile unsigned int i;
switch(__even_in_range(UCB0IV,4))
{
case 0: break; // Vector 0 - no interrupt
case 2: // Vector 2 - RXIFG
while (!(UCB0IFG&UCTXIFG)); // USCI_A0 TX buffer ready?
if (UCB0RXBUF==SLV_Data) // Test for correct character RX'd
P5OUT &=~ BIT6; // If correct, light LED
else
P5OUT |= BIT6; // If incorrect, clear LED
MST_Data++; // Increment data
SLV_Data++;
UCB0TXBUF = MST_Data; // Send next value
for(i = 20; i>0; i--); // Add time between transmissions to
// make sure slave can process information
break;
case 4:
break; // Vector 4 - TXIFG
default: break;
}
}
从机程序:
// MSP430F534x
// -----------------
/|\| |
/ | | |
// --| RST P5.6|-> LED
// | |
// | | P2.2|-> Master Data Out (UCB0SIMO)
// | | | |
// | P2.3|<- Master Data In (UCB0SOMI)
// | |
// Slave reset <-|P2.6
P2.1|-> Serial Clock Out (UCB0CLK)
//
//
// Bhargavi Nisarga
// Texas Instruments Inc.
// April 2009
// Built with CCSv4 and IAR Embedded Workbench Version: 4.21
//******************************************************************************
#include <msp430.h>
#define SPI_CLK BIT1
#define SPI_SIMO BIT2
#define SPI_SOMI BIT3
#define SPI_STE BIT6
// Ports
#define SPI_SEL P2SEL
#define SPI_DIR P2DIR
#define SPI_OUT P2OUT
#define SPI_REN P2REN
int main(void)
{
WDTCTL = WDTPW+WDTHOLD; // Stop watchdog timer
while(!(P2IN&0x02)); // If clock sig from mstr stays low,
// it is not yet in SPI mode
P2SEL |= BIT1+BIT2+BIT3; // P3.3,4 option select
UCB0CTL1 |= UCSWRST; // **Put state machine in reset**
UCB0CTL0 |= UCSYNC+UCCKPL+UCMSB; // 3-pin, 8-bit SPI slave,
// Clock polarity high, MSB
UCB0CTL1 &= ~UCSWRST; // **Initialize USCI state machine**
UCB0IE |= UCRXIE; // Enable USCI_A0 RX interrupt
__bis_SR_register(LPM4_bits + GIE); // Enter LPM4, enable interrupts
}
// Echo character
#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector=USCI_B0_VECTOR
__interrupt void USCI_B0_ISR(void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(USCI_B0_VECTOR))) USCI_B0_ISR (void)
#else
#error Compiler not supported!
#endif
{
switch(__even_in_range(UCB0IV,4))
{
case 0:break; // Vector 0 - no interrupt
case 2: // Vector 2 - RXIFG
while (!(UCB0IFG&UCTXIFG)); // USCI_A0 TX buffer ready?
UCB0TXBUF = UCB0RXBUF;
break;
case 4:break; // Vector 4 - TXIFG
default: break;
}
}