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6733用XT1设置时钟问题

芯片是6733,用XT1的32768外设晶体,设主频25M,仿真状态下运行,发现XT1LFOFFG = 0,但DCOFFG和OFIFG都 = 1,感觉很奇怪,为什么XT1错误标志没有反应,但DCO错误置位了,而且在时钟中断里,看下来也是已经在25M下运行没有错。不用XT1,用REFOCLK就没有这个问题

还有个奇怪的现象是如果我在启动晶振的程序while (SFRIFG1&OFIFG)    // Test oscillator fault flag 处设断点,程序就进入死循环,因为测到OFIFG = 1了,但如果一开始不设断点,直接运行,OFIFG 还是= 1,但会跑进主程序正常运行,这是仿真器的问题吗?

另外问一下各位高手,6733能不能接XT2?还是只能接XT1?(芯片引脚只有XIN,XOUT,没有XT2IN和XT2OUT),如果只能接XT1,能不能直接上25M的晶体?因为我看到XT1 有High-frequency 模式,XT1DRIVE设为11b时的描述是 Maximum drive capability and maximum current consumption for XT1 LF mode. XT1 oscillator operating range in HF mode is 24 MHz to 32 MHz.

下附晶振初始化的代码,请看看问题出在哪里?谢谢!

void setup_FLL(void)
{//启动晶振和时钟;
    
   // Open PMM registers for write
  PMMCTL0_H = PMMPW_H;            
  // Set VCore to new level
  PMMCTL0_L |= PMMCOREV_3;                                  
  // Wait till new level reached
  if ((PMMIFG & SVMLIFG))
    while ((PMMIFG & SVMLVLRIFG) == 0);      
  // Lock PMM registers for write access
  PMMCTL0_H = 0x00;

//用TX1做FLLREFCLK,主频选DCO
//      Initialize DCO to 25MHz
  
  UCSCTL6 &= ~(XT1OFF);                  // XT1 On
  
do
    {
        UCSCTL7 &= ~XT1LFOFFG;             // Clear XT1 fault flags
    } while (UCSCTL7 & XT1LFOFFG);         // Test XT1 fault flag

    __bis_SR_register(SCG0);               // Disable the FLL control loop
    UCSCTL3 = SELREF__XT1CLK;              // Set DCO FLL reference = TX1  
    UCSCTL0 = 0x0000;                      // Set lowest possible DCOx, MODx
    UCSCTL1 = DCORSEL_7;                   // Select DCO range 50MHz operation
    UCSCTL2 = FLLD_0 | 762;                // Set DCO Multiplier for 25MHz
                                           // (N + 1) * FLLRef = Fdco
                                           // (762 + 1) * 32768 = 25MHz
                                           // Set FLL Div(DCOCLKDIV) = fDCOCLK    
    
    __bic_SR_register(SCG0);               // Enable the FLL control loop

    // Worst-case settling time for the DCO when the DCO range bits have been
    // changed is n x 32 x 32 x f_MCLK / f_FLL_reference.. See UCS chapter in 5xx
    // UG for optimization.
    // 32 x 32 x 25 MHz / 32,768 Hz = 781250 = MCLK cycles for DCO to settle
    __delay_cycles(781250);  
    
while (SFRIFG1&OFIFG)                   // Test oscillator fault flag
  {
    UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG); // Clear XT2,XT1,DCO fault flags
    SFRIFG1 &= ~OFIFG;                          // Clear fault flags
  }
    
  UCSCTL4 |= SELA__XT1CLK+SELS__DCOCLKDIV + SELM__DCOCLK;//ACLK = XT1CLK;SMCLK = DCOCLKDIV;MCLK = DCOCLK    
}