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The interrupt latency is six cycles, starting with the acceptance of an interrupt request, and lasting until the start of execution of the first instruction of the interrupt service routine, as shown in Figure 1-4. The interrupt logic executes the following: 1. Any currently executing instruction is completed. 2. The PC, which points to the next instruction, is pushed onto the stack. 3. The SR is pushed onto the stack. 4. The interrupt with the highest priority is selected if multiple interrupts occurred during the last instruction and are pending for service. 5. The interrupt request flag resets automatically on single-source flags. Multiple source flags remain set for servicing by software. 6. All bits of SR are cleared except SCG0, thereby terminating any low-power mode. Because the GIE bit is cleared, further interrupts are disabled. 7. The content of the interrupt vector is loaded into the PC; the program continues with the interrupt service routine at that address.
退出中断的5个cycle做了下面的事情，
The return from the interrupt takes five cycles to execute the following actions and is illustrated in 1. The SR with all previous settings pops from the stack. All previous settings of GIE, CPUOFF, etc. are now in effect, regardless of the settings used during the interrupt service routine. 2. The PC pops from the stack and begins execution at the point where it was interrupted.
