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// Initialize DCO to 2.45MHz __bis_SR_register(SCG0); // Disable the FLL control loop UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx UCSCTL1 = DCORSEL_3; // Set RSELx for DCO = 4.9 MHz UCSCTL2 = FLLD_1 + 74; // Set DCO Multiplier for 2.45MHz // (N + 1) * FLLRef = Fdco // (74 + 1) * 32768 = 2.45MHz // Set FLL Div = fDCOCLK/2 __bic_SR_register(SCG0); // Enable the FLL control loop
// Worst-case settling time for the DCO when the DCO range bits have been // changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx // UG for optimization. // 32 x 32 x 2.45 MHz / 32,768 Hz = 76563 = MCLK cycles for DCO to settle __delay_cycles(76563);
