MSP430f5529捕获进不了中断

用的信号发生器给P1.2输入500Hz方波，高电平为3V，低电平为0V

#include <msp430f5529.h>

/*
 * main.c
 */
void  clock_init(void);
unsigned int overflow;
unsigned int start,end;
int T;

int main(void)
{
    WDTCTL = WDTPW + WDTHOLD;        //关闭看门狗
    clock_init();
    P1DIR &= ~BIT2;                                //P1.2(TA0.1)设置为输入
    P1SEL |= BIT2;                                //P1.2设置为第二功能，作为捕获源
    TA0CTL = TASSEL_2 + MC_2 + TACLR;     //选择SMCLK,连续增模式，开中断，TAR清零
    TA0CCTL1 = CAP + CM_2 + CCIS_0 + SCS + CCIE; //捕获模块1开启，选择TA0.0管脚作为捕获源，上升沿捕获，同步模式，开启捕获中断
    __bis_SR_register(GIE);       // Enter LPM0, enable interrupts                                                       //因为TimerA要用SMCLK，只能进入低功耗模式0休眠
	return 0;
}


#pragma vector = TIMER0_A0_VECTOR
__interrupt void TIMER0_A0_ISR(void)
{
	   T++;
	 switch(TA0IV)                                                    //TA中断向量查询
	 	 {
	          case 2:                                                         //是捕获中断  2为CCR1捕获中断向量值
	            if (TA0CCTL1 & CM0)                            //上升沿捕获
	            {
	                         TA0CCTL1 &=~ CM_1;
	                         TA0CCTL1 |= CM_2;                      //改为下降沿捕获
	                 start = TA0R;
	                  }
	                   if (TA0CCTL1 & CM1)                            //下降沿捕获
	            {
	                        TA0CCTL1 &=~ CM_2;
	                        TA0CCTL1 |= CM_1;                      //改为上升沿捕获
	                end = TA0R;
	                  }
	        break;

	            case 14:                                                //是溢出中断
	               overflow++;                                //溢出次数自加1
	            break;

	            default:
	            break;
	     }
}

/***********************时钟初始化函数，调整到12MHZ*******************/
void  clock_init(void)
{

	    UCSCTL3 = SELREF_2;                       // Set DCO FLL reference = REFO
	      UCSCTL4 |= SELA_2;                        // Set ACLK = REFO
	      UCSCTL0 = 0x0000;                         // Set lowest possible DCOx, MODx

	      // Loop until XT1,XT2 & DCO stabilizes - In this case only DCO has to stabilize
	      do
	      {
	        UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG);
	                                                // Clear XT2,XT1,DCO fault flags
	        SFRIFG1 &= ~OFIFG;                      // Clear fault flags
	      }while (SFRIFG1&OFIFG);                   // Test oscillator fault flag

	      __bis_SR_register(SCG0);                  // Disable the FLL control loop
	      UCSCTL1 = DCORSEL_5;                      // Select DCO range 16MHz operation
	      UCSCTL2 |= 249;                           // Set DCO Multiplier for 8MHz
	                                                // (N + 1) * FLLRef = Fdco
	                                                // (249 + 1) * 32768 = 8MHz
	      __bic_SR_register(SCG0);                  // Enable the FLL control loop

	      // Worst-case settling time for the DCO when the DCO range bits have been
	      // changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx
	      // UG for optimization.
	      // 32 x 32 x 8 MHz / 32,768 Hz = 250000 = MCLK cycles for DCO to settle
	      __delay_cycles(250000);

}