使用msp430FR5969 的Spi口时遇到的问题

注：

P1.6  MOSI   接设备 MOSI引脚

P1.7  MISO  接设备 MISO  引脚

P2.2 SCLK  接设备 SCLK  引脚

P3.0 CS       接设备 CS引脚

你好，

看起来你用的是3线的SPI，因为你的CS信号是受你程序控制的。

如你的代码所述，

uint8_t SPI_RW(uint8_t byte)
{
uint8_t rec_val; 
SPI_CS_L                   //    CS低为片选信号
UCB0TXBUF = byte; 
while((UCTXIFG & UCB0IFG) == 0);
while((UCRXIFG & UCB0IFG) == 0);

rec_val = UCB0RXBUF;
UCB0IFG &= ~UCRXIFG; 
SPI_CS_H
return rec_val; 
}

所以你说CS信号恢复为高，是因为你程序写的有问题，和SPI无关，下面给你一个SPI例程供你参考。

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//******************************************************************************
// MSP430F59xx Demo - eUSCI_A0, SPI 3-Wire Master Incremented Data
//
// Description: SPI master talks to SPI slave using 3-wire mode. Incrementing
// data is sent by the master starting at 0x01. Received data is expected to
// be same as the previous transmission TXData = RXData-1.
// USCI RX ISR is used to handle communication with the CPU, normally in LPM0.
// ACLK = 32.768kHz, MCLK = SMCLK = DCO ~1MHz. BRCLK = ACLK/2
//
//
// MSP430FR5969
// -----------------
// /|\ | XIN|-
// | | | 32KHz Crystal
// ---|RST XOUT|-
// | |
// | P2.0|-> Data Out (UCA0SIMO)
// | |
// | P2.1|<- Data In (UCA0SOMI)
// | |
// | P1.5|-> Serial Clock Out (UCA0CLK)
//
// P. Thanigai
// Texas Instruments Inc.
// Feb 2012
// Built with CCS V5.5
//******************************************************************************
#include <msp430.h>

volatile unsigned char RXData = 0;
volatile unsigned char TXData;

int main(void)
{
WDTCTL = WDTPW | WDTHOLD; // Stop watchdog timer

// Configure GPIO
P1SEL1 |= BIT5; // USCI_A0 operation
P2SEL1 |= BIT0 | BIT1; // USCI_A0 operation
PJSEL0 |= BIT4 | BIT5; // For XT1

// Disable the GPIO power-on default high-impedance mode to activate
// previously configured port settings
PM5CTL0 &= ~LOCKLPM5;

// XT1 Setup
CSCTL0_H = CSKEY >> 8; // Unlock CS registers
CSCTL1 = DCOFSEL_0; // Set DCO to 1MHz
CSCTL2 = SELA__LFXTCLK | SELS__DCOCLK | SELM__DCOCLK;
CSCTL3 = DIVA__1 | DIVS__1 | DIVM__1; // set all dividers
CSCTL4 &= ~LFXTOFF;
do
{
CSCTL5 &= ~LFXTOFFG; // Clear XT1 fault flag
SFRIFG1 &= ~OFIFG;
}while (SFRIFG1&OFIFG); // Test oscillator fault flag
CSCTL0_H = 0; // Lock CS registers

// Configure USCI_A0 for SPI operation
UCA0CTLW0 = UCSWRST; // **Put state machine in reset**
UCA0CTLW0 |= UCMST | UCSYNC | UCCKPL | UCMSB; // 3-pin, 8-bit SPI master
// Clock polarity high, MSB
UCA0CTLW0 |= UCSSEL__ACLK; // ACLK
UCA0BR0 = 0x02; // /2
UCA0BR1 = 0; //
UCA0MCTLW = 0; // No modulation
UCA0CTLW0 &= ~UCSWRST; // **Initialize USCI state machine**
UCA0IE |= UCRXIE; // Enable USCI_A0 RX interrupt
TXData = 0x1; // Holds TX data

while(1)
{
UCA0IE |= UCTXIE;
__bis_SR_register(LPM0_bits | GIE); // CPU off, enable interrupts
__delay_cycles(2000); // Delay before next transmission
TXData++; // Increment transmit data
}
}

#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector=USCI_A0_VECTOR
__interrupt void USCI_A0_ISR(void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(USCI_A0_VECTOR))) USCI_A0_ISR (void)
#else
#error Compiler not supported!
#endif
{
switch(__even_in_range(UCA0IV, USCI_SPI_UCTXIFG))
{
case USCI_NONE: break;
case USCI_SPI_UCRXIFG:
RXData = UCA0RXBUF;
UCA0IFG &= ~UCRXIFG;
__bic_SR_register_on_exit(LPM0_bits); // Wake up to setup next TX
break;
case USCI_SPI_UCTXIFG:
UCA0TXBUF = TXData; // Transmit characters
UCA0IE &= ~UCTXIE;
break;
default: break;
}
}

B0的SPI的baud分频也是使用UCA0MCTLW = 0？

上一楼的例子中用的是A0

初学者，请教一下，这个程序实现是单片机使用SPI 主机模式，发数据给你自己吗？自发自收？

是SPI 主机模式，不是自发自收