1. 此款LaunchPad是否可以通过板载的USB mini接口向上位的PC机传递数据？该怎样进行配置？
2. MSP432系列的eUSCI_B模块的I2C模式下UCBxBR0和UCBxBR1这两个寄存器是什么功能，该怎么配置？文档SLAU356A完全没说这两个寄存器是怎样配置bit rate的。
1. 此款LaunchPad是否可以通过板载的USB mini接口向上位的PC机传递数据？该怎样进行配置？
2. MSP432系列的eUSCI_B模块的I2C模式下UCBxBR0和UCBxBR1这两个寄存器是什么功能，该怎么配置？文档SLAU356A完全没说这两个寄存器是怎样配置bit rate的。
参见 P779 MSP432 用户手册,
I2C Clock Generation and Synchronization
The I2C clock SCL is provided by the master on the I2C bus. When the eUSCI_B is in master mode,
BITCLK is provided by the eUSCI_B bit clock generator and the clock source is selected with the
UCSSELx bits. In slave mode, the bit clock generator is not used and the UCSSELx bits are don't care.
The 16-bit value of UCBRx in registers UCBxBR1 and UCBxBR0 is the division factor of the eUSCI_B
clock source, BRCLK. The maximum bit clock that can be used in single master mode is fBRCLK/4. In multimaster
mode, the maximum bit clock is fBRCLK/8. The BITCLK frequency is given by:
fBitClock = fBRCLK/UCBRx
The minimum high and low periods of the generated SCL are:
tLOW,MIN = tHIGH,MIN = (UCBRx/2)/fBRCLK when UCBRx is even
tLOW,MIN = tHIGH,MIN = ((UCBRx – 1)/2)/fBRCLK when UCBRx is odd
The eUSCI_B clock source frequency and the prescaler setting UCBRx must to be chosen such that the
minimum low and high period times of the I2C specification are met.
During the arbitration procedure the clocks from the different masters must be synchronized. A device that
first generates a low period on SCL overrules the other devices, forcing them to start their own low
periods. SCL is then held low by the device with the longest low period. The other devices must wait for
SCL to be released before starting their high periods. Figure 24-16 shows the clock synchronization. This
allows a slow slave to slow down a fast master.
