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.title "50M21 FLASH READ ARRAY" .length 50 .width 120 .option X ************************************************************ * FLASH READ ARRAY (FL_RD) * * Additional Subroutine for TMS320F206 Flash Utilities. * * Revision 1.0 * * This program reads the flash memory with three different * * methods as follows: * * Fast read sequential * * Slow read sequential * * XOR read * * Each read method is CHECKSUM'ed for pass or fail. * * This program can be built to read the flash memory of a * * device that had been cleared, erased, programmed with * * a checker board pattern or programmed with a piece of * * code by changing the compiled switch "CS" below. * * * * * * Passed Parameters: * * FL_START Start address of flash range to be cleared.* * This address must start on a row start * * boundary. * * FL_END End address of flash range to be cleared. * * This address must end on a row end * * boundary. * * * * Returned Parameter: * * ACC = error code (0 if passed) * * * * This function can be compiled/assembled and used as a * * standalone test or used by the C2XX_BRX.ASM file. * * * * - For Stand alone, use the read_stdalone.cmd to compile * * and link. Note that when using this mode, the compile * * variable PRG2xx must be set to 0 also set the CNF to 1 * * (by using the CCS) before code is downloaded onto the * * target board since the code is supposingly downloaded on * * the on-chip B0 block * * * * - For using with the control module C2XX_BRX.ASM and * * the utility code Sutils20.asm, use the * * C2XX_BRX(_CCS).CMD to compile and link. Note that when * * using this mode, the compile variable PRG2xx must be set * * to 1. The PRG_2XX(W).EXE automatically set the CNF bit * * to 1 before downloading the C2XX_BBX.OUT onto the F206. * * * ************************************************************ .def FL_RD .global FL_RD .def _FL_RD .ref PARMS .global _FL_RD, START .include "fl_vars.h" .text PRG2xx .set 1 ;Set to 0 if not used by C2XX_BRX.ASM file * * STATISTICS VARIABLES FCSH .set 070h ;FAST CHECKSUM HI WORD FCSL .set 071h ;FAST CHECKSUM LO WORD SCSH .set 072h ;SLOW CHECKSUM HI WORD SCSL .set 073h ;SLOW CHECKSUM LO WORD XCSH .set 074h ;XOR CHECKSUM HI WORD XCSL .set 075h ;XOR CHECKSUM LO WORD CSH .set 076h ;CORRECT CHECKSUM HI CSL .set 077h ;CORRECT CHECKSUM LO
SPLK #FLST1,FL_START ;set flash start adrs SPLK #FLEND1,FL_END ;set flash end adrs LAR AR5,FL_START ;AR5 indicates which flash CALL RD3 ;Execute Triple Read on Flash0
BCND FailRD3_1,NEQ ;if Flash1 fails
LBL PASS NOP * B PASS B FL_RD ;looping
LBL FailRD3_0 IDLE B FailRD3_0 LBL FailRD3_1 IDLE B FailRD3_1
.endif
* * EXECUTE FAST CHECKSUM * LBL RD3 MAR *,AR5 ;ARP=>AR5 LAR AR0,#0 LACL FL_END ;ACC = FLASH END +1 SUBS FL_START ;ACC= FLASH LENGTH +1 * SUB #1 ;ACC -= 1 FLASH LENGTH SACL RPT_N ;SAVE FOR REPEAT COUNT SPLK #1,TEMP ;MPY FACTOR FOR CHECKSUM MPYK #0 ;PREG=0 LACL #0 ;ACC=0
CMPR 3 BCND OverFL0,TC RPT RPT_N ;FOR I=0;I<N;++ MAC #FLST0,TEMP ;CHECKSUM MEMORY B OverFL1 LBL OverFL0 nop RPT RPT_N ;FOR I=0;I<N;++ MAC #FLST1,TEMP ;CHECKSUM MEMORY
LBL OverFL1 APAC ; LAST SUM SACL FCSL ;SAVE LO CHECKSUM SACH FCSH ;SAVE HI CHECKSUM * * EXECUTE SLOW CHECKSUM * LAR AR1,FL_START ;SET START ADRS LAR AR0,FL_END ;SET END ADRS MAR *,AR0 MAR *+,AR1 LACL FL_END ;ACC=>END OF ARRAY + 1 ADD #1 * LBL SLOOP SUB #1 ;ACC=>NEXT WORD SACL FPTR ;SAVE POINTER TBLR TEMP ;DUMMY READ OF FLASH DATA TBLR TEMP ;SLOW READ OF FLASH DATA LACC SCSH,16 ;ACCH=SLOW CHECKSUM HI ADDS SCSL ;ACC = SLOW CHECKSUM ADD TEMP ;ACC += NEXT FLASH WORD SACL SCSL ;SAVE SLOW CHECKSUM LO SACH SCSH ;SAVE SLOW CHECKSUM HI LACL FPTR ;ACC=>CURRENT WORD * MAR *+ ;AR1=+1 CMPR 3 ;IF AR1 != AR0 BCND SLOOP,TC ;THEN CONTINUE LOOP * ; ELSE DONE SLOW CHECKSUM * * EXECUTE XOR CHECKSUM * SPLK #XORMASK,XOR ;initialize XOR LAR AR1,FL_START ;SET START ADRS LACL FL_END ;ACC=>END OF ARRAY + 1 ADD #1 * LBL XLOOP SUB #1 ;ACC=>NEXT WORD SACL FPTR ;SAVE POINTER XOR XOR ;SWITCH TO XOR PATTERN TBLR TEMP ;DUMMY READ OF FLASH DATA XOR XOR ;RESTORE ADRS TO CURRENT WORD TBLR TEMP ;SLOW READ OF FLASH DATA LACC XCSH,16 ;ACCH=SLOW CHECKSUM HI ADDS XCSL ;ACC = SLOW CHECKSUM ADD TEMP ;ACC += NEXT FLASH WORD SACL XCSL ;SAVE SLOW CHECKSUM LO SACH XCSH ;SAVE SLOW CHECKSUM HI LACL FPTR ;ACC=>CURRENT WORD * MAR *+ ;AR1=+1 CMPR 3 ;IF AR1 != AR0 BCND XLOOP,TC ;THEN CONTINUE LOOP * ; ELSE DONE SLOW CHECKSUM * * COMPARE CHECKSUMS * MAR *,AR1 ;ARP=>AR1 .if CS==0 LAR AR0,FCSH ;AR0=MASTER CHECKSUM .else LAR AR0,CSH ;AR0=MASTER CHECKSUM .endif
LAR AR1,FCSH ;AR1=FAST CHECKSUM HI CMPR 3 ;IF AR1 != AR0 BCND CS_ERROR,TC ; THEN TAKE ERROR TRAP LAR AR1,SCSH ;AR1=FAST CHECKSUM HI CMPR 3 ;IF AR1 != AR0 BCND CS_ERROR,TC ; THEN TAKE ERROR TRAP LAR AR1,XCSH ;AR1=FAST CHECKSUM HI CMPR 3 ;IF AR1 != AR0 BCND CS_ERROR,TC ; THEN TAKE ERROR TRAP .if CS==0 LAR AR0,FCSL ;AR0=MASTER CHECKSUM .else LAR AR0,CSL ;AR0=MASTER CHECKSUM .endif LAR AR1,FCSL ;AR1=FAST CHECKSUM LO CMPR 3 ;IF AR1 != AR0 BCND CS_ERROR,TC ; THEN TAKE ERROR TRAP LAR AR1,SCSL ;AR1=FAST CHECKSUM LO CMPR 3 ;IF AR1 != AR0 BCND CS_ERROR,TC ; THEN TAKE ERROR TRAP LAR AR1,XCSL ;AR1=FAST CHECKSUM LO CMPR 3 ;IF AR1 != AR0 BCND CS_ERROR,TC ; THEN TAKE ERROR TRAP * LACL #0 ;NO ERRORS RET ;RETURN TO CALLING SEQUENCE * LBL CS_ERROR LACL #0Ch ;CHECKSUM FAILS RET ;RETURN TO CALLING SEQUENCE * .end
************************************************************* ** Delay And Access Mode Subroutines ** * ** * TMS320F2XX Flash Utilities. ** * Revision: 2.0, 9/10/97 ** * Revision: 2.1, 1/31/98 ** * ** * Filename: sutils20.asm ** * Modified for F2xx : Sam Saba 12/24/96 ** * Changes20: Changed DELAY parameter passing to use AR6 ** * instead of a RAM location. ** * Changes21: Added conditional assembly statements to REGS ** * and ARRAY subroutines for F206 versus F24X. ** * ** * ** * Called by: These utilites are used by CLEAR,ERASE, ** * PROGRAM algorithms written for F2xx devices. ** * Function : DELAY - Delay loop specified by AR6. ** * REGS - Clears MODE bit of F_ACCESS0/1 to ** * access flash module control registers.** * ARRAY - Sets MODE bit of F_ACCESS0/1 to access** * the flash array. ** ************************************************************* .include "svar20.h" .def DELAY,REGS,ARRAY F24X .set 0 .sect "DLY"
************************************* *Delays as follows: * * LAR AR6,#N 2 Cycles * * CALL DELAY 4 Cycles * * RPT #DLOOP 2*(N+1) Cycles * * NOP DLOOP*(N+1) Cycles * * BANZ DLY_LP 4*N+2 Cycles * * RET 4 Cycles * * ------------------------ * * = DLOOP(N+1)+6*N+14 Cycles * * Set N and DLOOP appropriately to * * get desired delay. * *************************************
DELAY ;AR6 = OUTER LOOP COUNT DLY_LP RPT #DLOOP ;APPROX 5US DELAY NOP BANZ DLY_LP,*- ;LOOP UNTIL DONE RET ;RETURN TO CALLING SEQUENCE
.page ************************************************** * REGS - Clears MODE bit of F_ACCESS0/1 to ** * access flash module control registers.** ************************************************** .sect "REG" REGS SPLK #0000h,SPAD2 ***********The next instruction is for F240 only,************* .if F24X != 0 ;Assemble for F24X only. OUT SPAD2,F24X_ACCS ;Enable F24X flash reg mode. ;SPAD1 is dummy value. .endif
************************************************************** .if F24X = 0 ;Assemble for F206 only. LACC FL_ST SUB #4000h BCND reg1, geq ;if address>= 4000h,set ;set reg mode for flash1 array OUT SPAD2,F_ACCESS0 ;Change mode of flash0. RET reg1 OUT SPAD2,F_ACCESS1 ;Change mode of flash1. .endif RET ;RETURN TO CALLING SEQUENCE
.page ************************************************** * ARRAY - Sets MODE bit of F_ACCESS0/1 to access** * the flash array. ** ************************************************** .sect "ARY" ARRAY SPLK #0001h,SPAD2 ***********The next instruction is for F240 only,************* .if F24X != 0 ;Assemble for F24X only. IN SPAD1,F24X_ACCS ;Enable F24X flash array mode. ;SPAD1 is dummy value. .endif
************************************************************** .if F24X = 0 ;Assemble for F206 only. LACC FL_ST SUB #4000h BCND ary1, geq ;if address>= 4000h,set ;set reg mode for flash1 array OUT SPAD2,F_ACCESS0 ;Change mode of flash0. RET ary1 OUT SPAD2,F_ACCESS1 ;Change mode of flash1. .endif RET ;RETURN TO CALLING SEQUENCE .end
