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The PLLDIS pin enables bypassing the PLL for emulation and testing. This pin is essential for speeding up test time, which reduces chip cost. It cannot be multiplexed with another pin or general purpose input-output (GPIO) due to the various pin permutations required during test. The device can be used in bypass mode with only the crystal oscillator (PLL disabled);
参考说明为：
Once RTI OSC EN is programmed, the source of RTICLK is the oscillator for
all operating modes. When PLL STBY DIS is programmed, the PLL is
disabled upon entering STBY mode. This results in lower current
consumption. When the device is awakened from STBY mode, the PLL will
relock. An external interrupt to the CIM/IEM will trigger the PLL to start the
relock process. While the PLL relocks, the system clocks are held off for 4096
cycles. See Table 7 for the clocks available to the RTI module and the
corresponding PLL activities during standby mode.
