In terms of 8TB SSD, the bottle neck is the DDR which is illustrated as below:
a. The biggest wide temp DDR is 1GB x 8bit
b.8TB SSD needs 10pcs 1GB DDR(with pECC) on boards
c.80bit DDR as maximum but our controller only support 40bit DDR (DDR_DQ0~DDR_DQ39)
Question: How to realize the requirement?
1, Is there any dual channel DRAM controller or solution recommended to meet it?
2, Does the controller either need 80-bits or it needs more CS (Chip Select) or a combination of Address+BA+BG signals to select the new set of 5x DDR4 chips?
3, Currently the controller only has 2x CS -- and this is where the problem comes from. Additional problems are due to the extra load and branching on the Address and DATA. how to deal with it?