If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Fully compliant with USB 2.0 specification: TID #40390418
Integrated USB 2.0 UTMI compliant transceiver (PHY)
Supports USB high speed (HS, 480 Mbits/sec) and full speed (FS, 12 Mbits/sec)
Supports USB suspend/resume and remote wake-up operation
Supports USB device-unique serial number by using on-chip unique die ID
Supports eight configurable endpoints (four input and four output) with a user-programmable buffer size, in addition to the default control endpoint (endpoint 0):
Each endpoint can be configured for interrupt and bulk (double buffered) transfers.
All endpoints share the 4K byte data buffer implemented in the SPRAM (single port SRAM).
Microcontroller Unit (MCU)
Integrated 60-MHz 8051 microcontroller with two clocks per cycle (up to 30 MIPS)
Application code is loadable from either the USB host or the external EEPROM (via the I2C interface)
8K bytes of ROM for the boot loader
1152 bytes of RAM with multiple bank selectable capability for the internal data buffer (IDATA space)
40K bytes of RAM, configurable for either code or data space, which provides flexibility to the end product application:
32K byte code RAM with 8K byte sector buffer data space
16K byte code RAM with 24K byte sector buffer data space
8K byte code RAM with 32K byte sector buffer data space
Master I2C interface controller for external device accesses capable of 100 Kbits/sec or 400 Kbits/sec transfer speed.
Up to 13 GPIOs and three general-purpose open-drain outputs can be used for end product specific functions
