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我现在用MSP430FR5969内部的DCO可以配置时钟,如果用XT2外接4MHz晶振则无法起振。另外,没有用LFCLK,并且是悬空的
具体代码是
PJSEL0 |= BIT6 | BIT7; // For XT1 and XT2
// Disable the GPIO power-on default high-impedance mode to activate
// previously configured port settings
PM5CTL0 &= ~LOCKLPM5;
CSCTL0_H = CSKEY>>8 ; // Unlock CS registers
CSCTL1 = DCOFSEL_3 | DCORSEL; // Set DCO to 8MHz // Set DCO to 8MHz
CSCTL2 = SELS__DCOCLK | SELM__HFXTCLK;
CSCTL3 = DIVS__1 | DIVM__1; // Set all dividers to 1
CSCTL4 |= HFXTDRIVE_2;
CSCTL4 &= ~(LFXTOFF | HFXTOFF);
do
{
CSCTL5 &=~HFXTOFFG; // Clear XT2 fault flag
SFRIFG1 &= ~OFIFG; // 10000010
}while (SFRIFG1&OFIFG); // Test oscillator fault flag
CSCTL0_H = 0; // Lock CS registers
请问这是什么问题,参
你这开启X2了吗?
给你看个教程:怎样只用一个XT2晶振得到精确的高频
-------------------------------------------------------------
f(DCOCLK)=D*(N+1)*(f(FLLREFCLK)/n)
默认情况下,D=2,n=1,N是自己随意配置的整数。这里我要得到DCLCLK=16MHZ,我取的是D=16,N=1,n=8,当然你可以自己计算,不限于这个值。由DCOCLK/D=DCOCLKDIV,最终由DCOCLKDIV分频得到ACLK=31.5khz,当然跟32khz相差还挺大的,我也没有办法了。
另外也要扩大DCO倍频的赔率范围,5529数据手册上有指示的。特别要注意的是,这里你千万不能打开XT1,会出错的。最后,我帖上我的的程序,已经验证过了完全正确的
P1DIR |= BIT0;
P1SEL |= BIT0; //可以看ACLK的频率
P2DIR |= BIT2;
P2SEL |= BIT2; //SMCLK
P7DIR |= BIT7;
P7SEL |= BIT7; //MCLK
P5SEL |= BIT2+BIT3;
UCSCTL6 &= ~XT2OFF; //打开XT2
/*********************寄存器配置部分******************************/
__bis_SR_register(SCG0);
UCSCTL0 = DCO0+DCO1+DCO2+DCO3+DCO4;
UCSCTL1 = DCORSEL_4; //DCO频率范围在28.2MHZ以下
UCSCTL2 = FLLD_4 + 1; //D=16,N=1
UCSCTL3 = SELREF_5 + FLLREFDIV_3; //n=8,FLLREFCLK时钟源为XT2CLK;DCOCLK=D*(N+1)*(FLLREFCLK/n);DCOCLKDIV=(N+1)*(FLLREFCLK/n);
UCSCTL4 = SELA_4 + SELS_3 +SELM_3; //ACLK的时钟源为DCOCLKDIV,MCLK\SMCLK的时钟源为DCOCLK
UCSCTL5 = DIVA_5 +DIVS_1; //ACLK由DCOCLKDIV的32分频得到,SMCLK由DCOCLK的2分频得到
//最终MCLK:16MHZ,SMCLK:8MHZ,ACLK:32KHZ
__bic_SR_register(SCG0); //Enable the FLL control loop
/**********************************************************************/
__delay_cycles(8192);
do
{
UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG); //Clear XT2,XT1,DCO fault flags
SFRIFG1 &= ~OFIFG; //Clear fault flags
}while (SFRIFG1&OFIFG);