DRV8245-Q1: Questions about SPI Control and Power-on Initialization for DRV8245-P Chip

Hello TI Engineers and Community,

I am evaluating and using the DRV8245-P motor driver and have a few questions regarding the SPI variant that I hope you can clarify.

My understanding is that for the SPI variant of the DRV8245, after the nSLEEP pin is released, the chip's default state is to have the drivers disabled (outputs in a high-impedance state). At this point, control instructions must be sent via the SPI interface to enable the outputs and initiate driving.

Based on this understanding, I would like to confirm the following two points:

1. Initial Configuration and Latching Mechanism:
   Is my understanding correct: After I configure all the control registers (e.g., Control Register 1 CTRL1) via the SPI interface during the initial power-up sequence, these configuration values are latched by the chip. Even if I subsequently disconnect the SPI controller (e.g., hold the SPI chip select SCS high, or the SPI bus becomes inactive), the chip will continue to operate based on the last latched configuration (e.g., maintaining output drive)? In other words, is SPI communication only necessary for configuration and not required continuously?

2. Power-on Initialization Requirement:
   Does this mean that every time the chip powers up from low to high, I must perform a complete register configuration via the SPI bus? Otherwise, will the driver remain in the default disabled state? Or, under certain configurations (e.g., using non-volatile memory?), can the chip remember the previous settings?

To summarize, my core confusion is: Is SPI control only necessary for a one-time configuration after "wake-up," after which it can be disconnected, and does this "one-time configuration" need to be repeated on every power cycle?

Thank you very much for your time and assistance! Please correct me if my understanding is mistaken.