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DRV8718S-Q1EVM: Regarding the issue of configuring DRV8718S

chou shingo
Prodigy 10 points

Part Number: DRV8718S-Q1EVM

Hi,
   I've connected an MCU to one DRV8718 chip via SPI. The SPI configuration is: MSB first, 1MHz, CPOL=0, CPHA=1, 16bits.
  I have two points of doubt, as follows:
   1. I'm trying to read the IC_STAT2 Register (Address = 5h) only, the received data is 0xC002. This means that the SCLK_FLT has malfunctioned. However, the number of SCLK pulses in this frame are equal to 16. The waveform graph is as follows, What is going on? image.png   2. To control individual high-side(GH5) and low-side(GL6) external MOSFETs, I'm trying to write 0x90  into the BRG_CTRL2 register(Address = Ah), but the peripheral circuit did not functioning properly.
Are there any other registers that need to be configured? The peripheral circuit is shown as following: image.png
  • 0
    TI__Mastermind 45365 points

    您好，

    已经收到了您的案例，调查需要些时间，感谢您的耐心等待。

  • 0
    TI__Mastermind 40495 points
    chou shingo 说：
     I've connected an MCU to one DRV8718 chip via SPI. The SPI configuration is: MSB first, 1MHz, CPOL=0, CPHA=1, 16bits.
      I have two points of doubt, as follows:
       1. I'm trying to read the IC_STAT2 Register (Address = 5h) only, the received data is 0xC002. This means that the SCLK_FLT has malfunctioned. However, the number of SCLK pulses in this frame are equal to 16. The waveform graph is as follows, What is going on? image.png

    This may indicate the issue happened during the previous frame. After power up and nSLEEP = 1, wait for > tWAKE 1 ms before starting an SPI transaction. As well as, be sure to keep nSCS always high without a low going pulse during power on or wake up. If nSCS toggles without SPI SCLK transactions an SCLK_FLT will be reported. 

    chou shingo 说：
    2. To control individual high-side(GH5) and low-side(GL6) external MOSFETs, I'm trying to write 0x90  into the BRG_CTRL2 register(Address = Ah), but the peripheral circuit did not functioning properly.
    Are there any other registers that need to be configured?

    The DRVOFF/nFLT pin is multi-function and at power on this pin will be a DRVOFF control. This pin must not be externally pulled up. If it was pulled up the outputs will be disabled. If nFLT function is desired then the DRVOFF_nFLT bit in IC_CTRL2 register must be set to 1b. In this mode an external pull up such as 10 kΩ will be required for fault status reporting on this pin. 

    The peripheral circuit is shown as following:

    Nothing else need to be configured other than the BRG_CTRL2 Register.