BQ25960EVM: Question about the schematic diagram

First, I highly recommend using 2x BQ25960 in parallel by configuring each as a standalone device and controlling them separately, rather than configuring them as primary and secondary devices and using the SYNC pin.

This approach is the most common way that customers use 2x BQ25960, and we have much better validation coverage for using two devices in standalone mode. Additionally, there’s no performance benefit to the primary/secondary configuration, and almost all protections are disabled on the secondary device in this configuration since they’re handled by the primary device. There’s no need to connect the SYNC pin between the devices when each are in standalone mode. Overall, a dual-standalone configuration is a simpler, more flexible, and better-supported approach.

We used two BQ25960 IC,Among them, U1000 was the primary charger, while U1001 was the secondary charger.

the secondary BQ25960 batp/batn_srp pin connected to the GND in the datasheet but batp/batn_srp pin connected to the battery terminal in the EVM.

So, how should this be connected?

BATP/BATN_SRP can be tied to GND on the secondary device, as shown in the datasheet. On the EVM, BATP and BATN of the secondary device are connected to the battery terminals for evaluation flexibility.

2、On primary BQ25960, since there is a certain distance between the current sampling resistor and the negative terminal of the battery, there will be a voltage drop.The SRP/BATN pin simultaneously samples the terminal voltage of the battery negative terminal and the current through the resistance. Whether the detected terminal voltage of the battery negative terminal or the current is inaccurate?

If the negative terminal of the battery and sense resistor are connected relatively close to each other and by a large copper pour, I wouldn’t expect there to be a significant delta between the negative terminal of the battery and the sense resistor. Please note that VBATOVP, VOUTOVP, IBATOCP, VBATADC, VOUTADC, and IBATADC all have associated accuracy specs. For reference, please see the below image showing the BATN connection on the EVM. Please note that the positive side of the sense resistor and the negative terminal of the battery share a copper pour, and BATN is Kelvin-connected to the positive sense resistor pad.

ks said:

3、Why the secondary BQ25960 TSBAT pull-up power supply  set to REGN_M instead of REGN_S?

TSBAT can be pulled up to either REGN_M or REGN_S for evaluation flexibility.

Feel free to let me know if you have any other questions.

Hello,

I've reviewed the BQ25960 portion of the schematic. I have a few questions:

• PMID has 2x 10uF on the master and slave. It's highly recommended to have 10uF on PMID. 20uF on PMID is expected to have a negative impact on efficiency. Could this be changed?
• VBUS has 10uF on the master and slave. It's highly recommended to have 1uF on VBUS. This is also expected to have a negative impact on efficiency. Could this be changed?
• BATP and BATN of the master and slave are connected. This is okay, but I'm just curious if they will use this on both chargers? Sometimes, customers only use this on one of the chargers.

Please see my other comments below:

• VOUT has 2x 10uF on the master and slave. It's recommended to have 22uF on VOUT. This is acceptable.
• VAC2 of the master and VAC1/2 of the slave are connected to VBUS.
• /INT, SDA, and SCL are each pulled up and connected to the MCU.
• 3x 22uF capacitors are used on CF1 and CF2.
• A 220nF is connected between CDRVH and CDRVL_ADDRMS for the master and slave.
• BATP is connected to the positive battery terminal through a 100ohm resistor for the master and slave.
• BATN is connected to the negative battery terminal and positive side of the sense resistor for the master and slave.
• ACDRV1 of the master is connected to ACFET1 (no RBFET in design).
• ACDRV2 of the master and ACDRV1/2 of the slave are tied to GND, since the master is controlling the ACFET.
• REGN has a 4.7uF capacitor on the master and slave.
• SRN_SYNCIN is connected to the bottom of the 2mohm sense resistor for the master and slave.
• CDRVL_ADDRMS of the master has a 6.2k resistor, which sets the master's I2C address to 0x67 and mode to standalone.
• CDRVL_ADDRMS of the slave has a 14k resistor, which sets the slave's I2C address to 0x66 and mode to standalone.

1、Should the addresses all be set to the standalone mode as listed in the table?

Yes, the configuration of each device should be set to standalone mode. This appears to be correct in the schematic. The >75k option can be utilized by not placing an address resistor on one of the chargers.

2、The USB and BAT temperature are read by the platform's main PMIC, therefore BQ25980 TSBUS and TSBAT PIN is possible to be float or some other simple method?

Yes, TSBUS and TSBAT can float if not being used, as long as these features are disabled in REG0x0A via I2C.

Please feel free to share any changes to the schematic, and I'd be happy to review them.

The functionality of the charger will not be affected by tying BATP, BATN, and SRN_SYNCIN to GND. 

This charger won't ever trip VOUTOVP, VBATOVP, or IBATOCP, but these protections will be provided by the other charger. VOUTUVLO and VOUTPRESENT, which are conditions for I2C communication and enabling the converter, are sensed at VOUT, not at BATP and BATN.