LM3410-Q1:Schematic Review and Technical Issue Discussion

Part Number: LM3410-Q1
Other Parts Discussed in Thread: LM3410

  Our company is currently utilizing your LM3410 IC in a T-BOX project, where it functions as a charging IC for a backup 0.1C NiMH battery with 600mAh capacity. The input power is a stable 5V output from a primary DC-DC converter.

We are encountering an issue where some ICs are being damaged during the initial charging cycle of the backup battery. For the failed units, we measured approximately 300Ω resistance between VIN pin and GND using a multimeter, while normal chips typically show resistance in the MΩ range. We would appreciate your assistance with the following questions:

  1. Could the multimeter measurement method for internal resistance potentially damage the IC?

  2. Can the measured internal resistance reliably indicate chip condition or failure severity? (Note: For failed chips, the in-circuit resistance measurements aren't consistent - some show values fluctuating between 900Ω to 2KΩ, yet some still function normally.)

  3. Have you encountered similar cases in other projects that might provide reference solutions?

  4. Could you please review our schematic and PCB design to check for any problematic circuits or design flaws that might cause chip damage?

  5. If question 2's premise holds true (that resistance indicates chip health), would ICs with lower-than-normal resistance (though currently functioning) be more prone to future failure?

We would greatly appreciate your technical analysis and suggestions regarding these matters.

  • 您好,

    已经收到了您的案例,调查需要些时间,感谢您的耐心等待。

  • 1. No
    2. It can reliably indicate failure, but not necessarily to determine the severity of a failure

    I need wave forms to be able to help you properly diagnose this issue. Additionally, I don't see any reverse battery protection or ESD protection diodes on the schematic... Can you please capture the transient event in which this issue is occurring?

    I would like to see Vin, Vout, VSW, and IL on the same scope shot. 

  •   Due to the randomness of the fault, we haven't yet been able to capture the waveform at the exact moment when the fault occurs. We have measured the waveforms at the VBAT pin, VIN pin, and SW pin. In addition, we added an RC snubber (5.1Ω and 1.5nF) between the SW pin and the ground in close proximity, which can effectively reduce the fault rate. We would like to know the principle and root cause of the fault, and we hope this information will be helpful for your analysis.

  • I am not familiar with the topology you are attempting to use... C53 looks like it is AC coupling your signal to VOUT which could explain the ringing you are seeing on the switch node. Also, I have seen similar ringing when the PCB layout is not optimized properly. 

    Lets start by bypassing C53.

  • We are currently working on a SPEIC circuit, but there are issues with the design. We plan to replace D33 with an inductor. Could you recommend the inductance value? Should both the inductance and current rating be the same as L7? Currently, L7 is 2.2uH. Could you also advise on how to modify the circuit to properly implement a SPEIC circuit?

  •   Today, we replaced D33 with a 4.7uH inductor and also changed L7 to 4.7uH. Due to package constraints, we could only use the inductors shown in the figure. The measured waveform is as depicted. After replacing the diode with an inductor, the circuit now operates as a SEPIC topology, which is essentially the same as the circuit in Figure 26 of the datasheet. However, why is the ringing even worse? We’d appreciate your advice on what modifications we should make. (Later, we also tried changing both inductors to 2.2uH, but the ringing waveform remained largely similar.)

  • Here is a tutorial on designing SEPIC converters

    https://www.ti.com/lit/an/snva168e/snva168e.pdf

    what is the PPM ID for this project?