The current issue is that when the entire system is powered off using the sleep command, VOUT_LDO1 & LDO2 rises to around 2V after about 170ms and then falls back.
A: However, this does not happen when powering off using the ON/OFF power supply. I understand the difference lies in the downstream load.
B: I have tested some data. Please let me know if anything is unclear. I hope this issue can be resolved quickly. Thank you.
I see that the input voltage to the PMIC is slowly dropping. What is value of VCCA when LDO1 and LDO2 voltage starts to rise again?
What is the downstream load doing at this time? Can you do an experiment with downstream load disconnected?
When the PMIC input voltage drops far enough, the internal pull-down / discharge resistors of the LDOs disengage. I think the load is back driving this voltage.
1. 2.2V（VCCA--->5V）
2. These outputs are directly connected to the SOC and require insurance, but I don't think the load can withstand 170 ms. When the LDO spikes again, it will definitely be without power.
3.Pay attention to the moment when EN is pulled low but VCCA hasn't dropped to 0V yet — is it a secondary startup? But I haven't found a reasonable logic for it.
1. 2.2V（VCCA--->5V）
2. These outputs are directly connected to the SOC and require insurance, but I don't think the load can withstand 170 ms. When the LDO spikes again, it will definitely be without power.
3.Pay attention to the moment when EN is pulled low but VCCA hasn't dropped to 0V yet — is it a secondary startup? But I haven't found a reasonable logic for it.
1. 2.2V（VCCA--->5V）
2. These outputs are directly connected to the SOC and require insurance, but I don't think the load can withstand 170 ms. When the LDO spikes again, it will definitely be without power.
3.Pay attention to the moment when EN is pulled low but VCCA hasn't dropped to 0V yet — is it a secondary startup? But I haven't found a reasonable logic for it.
