Part Number: BQ76952
When powered on, the DDSG and DCHG pins are configured as 0x2A, and the pins automatically output a high level. How can I configure them to output a low level? Can I map the DDSG and DCHG pins by controlling CHG and DSG?
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Part Number: BQ76952
When powered on, the DDSG and DCHG pins are configured as 0x2A, and the pins automatically output a high level. How can I configure them to output a low level? Can I map the DDSG and DCHG pins by controlling CHG and DSG?
The DDSG and DCHG pins when configured correctly, should follow the CHG/DSG FET driver states. I have shared FAQ above that should help with configuration.
The FET Status Register should show if the DDSG/DCHG pin have been asserted or not.