TPS546E25: TPS546E25: Request for a Four-Phase SIMPLIS Stacking Model or an Authorized Unencrypted Model

Part Number: TPS546E25
Other Parts Discussed in Thread: TPS546C25

Hello TI Team,

I am a master’s student at Sichuan University, China. I am currently working on a non-commercial power-electronics project for a postgraduate electronic design competition.

Our project uses four TPS546E25 devices to implement a four-phase interleaved synchronous buck converter. The main design requirements are:

• Input voltage: 6 V or 12 V

• Output voltage: 0.9 V

• Nominal output current: 120 A

• Load transient: 30 A to 200 A

• Load slew rate: approximately 500 A/µs

• Switching frequency: 800 kHz per phase

• Target phase sequence: 0°, 90°, 180°, and 270°

I am using the official TPS546C25/TPS546E25 SIMPLIS model package, SLVMEC4, available on the TI product page.

According to the TPS546E25 datasheet and the application brief “Achieving Higher Output Current by Stacking TPS546E25 and TPS546C25 DC/DC Converters,” I configured the circuit as one primary device and three secondary devices. I also connected the TRIGGER and ISHARE pins together and connected the VOSNS and GOSNS pins of all four devices to the same output-sense point.

I selected the MSEL1, MSEL2, VSEL/FB, and PMB_ADDR/VORST# resistors according to the four-phase pin-strap tables in the datasheet. However, in my current SIMPLIS simulation, changing these configuration resistors does not generate the expected four-phase interleaved operation. The four SW-node waveforms remain nearly in phase instead of being separated by 90 degrees.

Because the internal SIMPLIS model is encrypted, I cannot determine whether the following functions are implemented in the public model:

1. Primary and secondary device detection through MSEL1

2. Four-phase stack-position detection through PMB_ADDR/VORST#

3. TRIGGER pulse generation and propagation between devices

4. Automatic 90-degree phase interleaving

5. Phase-current sharing through ISHARE

Could you please help clarify the following questions?

1. Does the public SLVMEC4 SIMPLIS model support two-, three-, and four-device stacking?

2. Does it decode the external pin-strap resistors and automatically assign the phase positions?

3. If these functions are supported, could TI provide a working four-phase SIMPLIS schematic, testbench, or netlist showing the correct connections and resistor values?

4. If the public model supports only single-phase operation, could TI provide an updated full-featured SIMPLIS model that includes TRIGGER, ISHARE, stack-position decoding, and interleaved operation?

5. Is an authorized unencrypted or unlocked model available for academic use, possibly through a local TI FAE or under an NDA or other confidentiality agreement?

6. If an unencrypted model cannot be provided, could TI provide a parameterized or protected four-phase-capable model that allows the stack position and phase shift to be configured externally?

I am not attempting to bypass the protection of the TI model. I am requesting an officially authorized model or simulation method that can reproduce the actual four-phase stacking behavior described in the TPS546E25 datasheet.

The purpose of the simulation is to verify:

• The 0°/90°/180°/270° switching sequence

• Steady-state current sharing among the four phases

• Output-ripple cancellation

• The 30 A to 200 A load-transient response

• The influence of MSEL2 compensation settings, inductance, and output capacitance

I can provide my four-device SIMPLIS schematic, pin-strap resistor table, F11 simulation settings, and the four SW-node waveforms if they are required for review.

Any model or information provided by TI will be used only for this academic competition project, and I am willing to comply with the applicable TI license and confidentiality requirements.

Thank you very much for your support.

Best regards,

Jiawei Xie
Master’s Student
Sichuan University, China