BQ76PL455A－节电池断线检测问题

This test connects an internal resistor between every 2 adjacent sense leads. This feature is called ‘squeeze’ in the data manual. The cell channels are sampled both before and after enabling the squeeze function to compare for an appropriate change in voltage.  The host controller is responsible for controlling the process and determining if enough change was detected.

BatBroken is done with the following sequence:

1. Read CBENBL register and check that the value is 0x0000 to ensure the internal squeeze resistors are disabled.
2. Sample all cells and store the sampled valued to compare later.
3. Enable the squeeze function by setting the TSTCONFIG[EQ_SQUEEZE_EN] bit. This will also disable all EQ pin outputs.
4. Enable one half of the internal resistors by writing 0xAAAA (all odd channels) to the CBENBL register.
5. Wait ADCWAIT for the cell inputs to be able to respond to an actual open wire condition. ADCWAIT will depend on the component selection in the cell input filter circuit.[TV1]  
6. Sample all cells and compare to the sampled value stored earlier. If any cell has deviated a significant amount from the valued stored in step #2, then that odd cell has an open wire.
7. Enable one half of the internal resistors by writing 0x5555 (all even channels) to the CBENBL register.
8. Wait ADCWAIT for the cell inputs to be able to respond to an actual open wire condition. This will depend on the component selection in the cell input filter circuit.
9. Sample all cells and compare to the sampled value stored earlier. If any cell has deviated a significant amount from the valued stored in step #2, then that even cell has an open wire.
10. Write 0x0000 to the CBENBL register to ensure the internal squeeze resistors are disabled.
11. Disable the squeeze function by clearing the TSTCONFIG[EQ_SQUEEZE_EN] bit. This will also re-enable all EQ pin outputs.

Possible Faults and post conditions:

-       ADC OV fault indicated by FAULT_SUM[OV_FAULT_SUM] (address 0x52-53) set, and corresponding cell OV faults set in FAULT_OV[OV_FAULT] (address 0x56-57).

-       ADC UV fault indicated by FAULT_SUM[UV_FAULT_SUM] (address 0x52-53) set, and corresponding cell UV faults set in FAULT_UV[UV_FAULT] (address 0x54-55).

-       Window comparator OV fault indicated by FAULT_SUM[CMPOV_FAULT_SUM] (address 0x52-53) set, and corresponding comparator OV faults set in FAULT2_OV[CMPOV_FAULT] (address 0x5C-5D).

-       Window comparator UV fault indicated by FAULT_SUM[CMPUV_FAULT_SUM] (address 0x52-53) set, and corresponding comparator UV faults set in FAULT2_UV[CMPUV_FAULT] (address 0x5A-5B).

Note: ADCWAIT is the amount of time required to see a change on the input in the open wire condition. An open could occur at any point in the sample path, however the worst case duration would be if the open wire break occurred somewhere between the input filter cap and the cell. A simplified diagram of the SQUEEZE resistor in relation to the input filter cap is shown below.