我按照datasheet的典型应用连接，为什么tps60100的输出却为5v
pulse-skip mode
In pulse-skip mode (SKIP = high), the error amplifier disables switching of the power stages when it detects an
output higher than 3.3 V. The oscillator halts. The IC then skips switching cycles until the output voltage drops
below 3.3 V. Then the error amplifier reactivates the oscillator and switching of the power stages starts again.
The pulse-skip regulation mode minimizes operating current because it does not switch continuously and
deactivates all functions except bandgap reference and error amplifier when the output is higher than 3.3 V.
When switching is disabled from the error amplifier, the load is also isolated from the input. SKIP is a logic input
and should not remain floating. The typical operating circuit of the TPS60100 in pulse skip mode is shown in
Figure 1.
constant-frequency mode
When SKIP is low, the charge pump runs continuously at the frequency fOSC. The control circuit, fed from the error amplifier, controls the charge on C1F and C2F by driving the gates of the FETs T12/T13 and T22/T23, respectively. When the output voltage falls, the gate drive increases, resulting in a larger voltage across C1F and C2F. This regulation scheme minimizes output ripple. Since the device switches continuously, the output noise contains well-defined frequency components, and the circuit requires smaller external capacitors for a given output ripple. However, constant-frequency mode, due to higher operating current, is less efficient at light loads than pulse-skip mode.
