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BQ76940 + BQ78350-R2 AFE OVRD 機制

user4360882
Prodigy 70 points
Other Parts Discussed in Thread: BQ76940, BQ78350-R1

大家好,

目前使用BQ76940 + BQ78350-R2  方案遇到AFE OVRD的問題  (兩chip 的alert pin 是接再一起的)

根據BQ76940  DATASHEET  描述， 使用外部電路拉高 Alert pin 會使 CHG, DSG  OFF 

但根據BQ78350-R1  TRM描述，AFE ALERT OVRD Protection 可以偵測BQ76940 的 alert pin 被拉高的狀況，並且允許設置 " Delay time " 

那麼當外部拉高alert pin ，應該會立即使 CHG, DSG  OFF ，BQ78350-R2 所設定的 " Delay time " 功能就無法執行了吧?

而實際量測狀況也是如此， 外部拉高alert pin, CHG, DSG  OFF ，BQ78350-R2 所設定的 " Delay time " 沒有執行。

另一問題 ，  BQ78350-R2 的 alert pin  是Input pin ，且應該無法分辨 alert pin 是被外部拉高還是BQ76940拉高的吧，那麼他的功能是什麼 ?

BQ78350-R1 DATASHEET 完全沒有描述。

  • 0
    Guru 63421 points
    The ALERT pin serves as an active high digital interrupt signal that can be connected to a GPIO port of the host microcontroller. This signal is an OR of all bits in the SYS_STAT register.
    In order to clear the ALERT signal, the source bit in the SYS_STAT register must first be cleared by writing a “1” to that bit. This will cause an automatic clear of the ALERT pin once all bits are cleared.
    The ALERT pin may also be driven by an external source; for example, the pack may include a secondary overvoltage protector IC. When the ALERT pin is forced high externally while low, the device will recognize this as an OVRD_ALERT fault and set the [OVRD_ALERT] bit. This triggers automatic disabling of both CHG and DSG FET drivers. The device cannot recognize the ALERT signal input high when it is already forcing the ALERT signal high from another condition.