If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Is the testing being done with battery cells connected to the board? I didn't see an answer to this in your response. Are any of the components on the board damaged?
I do see some issues in the schematic, although these may not be related to the ESD test failing:
The REGIN pin capacitor should be 22nF. It looks like it is 22pF in the image.
The cell input resistors (VCx pins) have a maximum resistor value of 100 Ohms. 200 Ohms is shown on the schematic.
The CP1 pin capacitor likely needs to be bigger (2.2uF) since there are so many FETs in parallel.
On our hardware, we use ESD protection capacitors between PACK+ and PACK- and across the protection FETs
