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Hello TI team
I encountered several problems during the testing process. The first is that the chip will have abnormal waveforms when operating at 300kHz, and the gate oscillation is obvious. The second is that the maximum load current 20A cannot be reached. The last one is the intermittent rest of the chip when it is unloaded.
Hope you can give some good solutions, thank you very much.
Hi
从你描述看很可能是layout不好,特别是带载能力下降,要特别注意功率回路尽量小,以及电流保护走线。
layout建议严格参考datasheet第36~40页描述来做。
I have done according to the datasheet, but there will still be concussion problems, what other possible reasons
I really need your help,thanks
HI
将电路放上来看看? 或者你借助芯片官网在线仿真webench确认一下电路。
一般不建议芯片和MOS电感等分别放在板子正反两面,从你描述看仍重点确认layout。
Hello, this is a designed circuit, drawn according to the datasheet. The PCB is also designed according to the datasheet, with the MOS inductor on top and the chip on the back.
Besides LAYOUT, are there any other possible causes for these phenomena?
HI
完全参照datasheet的电路,说明不是电路问题,剩下的主要就是确认功率电感没有质量问题,饱和电流足够。如果这些都没有问题,剩下就只有layout。
从你上面的波形看,驱动出现大小波吗? 而且空载出现异常,具体异常能说详细说下。
At 300kHz, large and small waves appear, and the other frequencies are only the gate oscillation is more obvious. The anomaly in no-load is that the waveform has a radian after power-on, and then the waveform disappears for a period of time, but during this period the output is still normal, as if the chip is working intermittently. In addition, even 0.1A load current will lead to abnormal output and waveform disorder.
Then how do I need to improve the Layout? This version is already drawn according to the datasheet. In addition, I would like to ask whether it is possible to cut off the DCR detection loop. I suspect that DCR has caused concussion feedback on the gate. Can the CS- and CS+ ports of the chip be suspended?
So whether it is possible to cut off the DCR detection loop. I suspect that DCR has caused concussion feedback on the gate. Can the CS- and CS+ ports of the chip be suspended?