4S2P的电池包在对通讯和P+,P-打静电接触+/-8KV时会触发芯片复位,请帮忙看下是哪里有问题谢谢!下图分别是原理图和通讯和P+,P-部分的PCB走线以及打静电时P+,P-掉电20ms触发复位的波形。



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您好,请参考下面内容
The layout is not ideal, it should have a solid ground plane to help absorb the ESD as much as possible and the caps on PACK+ to PACK- should have as short and thick traces as possible. We see the biggest improvements by adding the ground plane. Also try increasing C19 and C20 to absorb more of the voltage before it is applied to the gauge.