TPS650332-Q1: I2C_INVALID_ADDR_ERR will happen when read 2Ch register

Hi team:

I searched for relevant issues in the above link.
In the question, it is mentioned that "Enabling I2C CRC enables the I2C-INVALID-ADDR-ERR check" and "The GUI automatically reads register 0x4A (EEPROM-PROG-CMD) as part of the register map, but the device sees this register as an invalid address to read (all other registers in the TPS650332-Q1 register map are valid addresses)".
In my design, I also enabled I2C CRC. But 0x4A is actively read, not automatically read by the chip. When I block the code reading 0x4A, "I2C-INVALID-ADDR-ERR" no longer occurs; But does the 0x4A register affect I2C CRC detection? Can I block reading code of 0x4A?