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TPS22811: 问题咨询

Part Number: TPS22811


关于TPS22811芯片的问题点如下:

1. 实际应用中,PG和PGTH 具体监控原理是什么?是否为必选?

2. PG和PGTH的电压如何正确理解?其中PGTH上升电压(1.2V)是否和UVLO的上升电压(1.2V)原理一致? 

3.如果问题1中,PG和PGTH为必选,如何配合电压进行电阻的匹配?如输出3.3V。

4.正常工作时,PG和PGTH应为高电平,但实际测试评估板均为低电平,但输出电压正常。该现象是否正常?如实际应用中有无影响?

4.1 测试评估板时,欠压和过压电压已配置成功并验证可行,输出电压正常(VIN 3.3V)。PG上拉至VIN(J13 为23连接),PGTH上拉至Vout(J2为12连接)。此时测量PG电压0V,PGTH电压0.35V(1.该0.35V是否可理解为3.3V的电阻分压?理论计算电阻分压为0.35V;2.如为电阻分压,同时更改R12为40K,R13为27K,根据分压PGTH应为1.2V,但实际0V)。

  • 您好

    1. 实际应用中,PG和PGTH 具体监控原理是什么?是否为必选?

    关于监控原理请参考datasheet中的说明

    7.3.7 Power-Good Indication (PG) The TPS22811x provides an active high digital output (PG) which serves as a power-good indication signal and is asserted high depending on the voltage at the PGTH pin along with the device state information. The PG is an open-drain pin and must be pulled up to an external supply. After power up, PG is pulled low initially. The device initiates a inrush sequence in which the HFET is turned on in a controlled manner. When the HFET gate voltage reaches the full overdrive indicating that the inrush sequence is complete and the voltage at PGTH is above VPGTH(R), the PG is asserted after a de-glitch time (tPGA). PG is de-asserted if at any time during normal operation, the voltage at PGTH falls below VPGTH(F), or the device detects a fault (except overcurrent). The PG de-assertion de-glitch time is tPGD.

    如果您想直观理解请参考下图中,PG和PGH有相关信号到HFET Control进而影响到后续。所以建议您做相关配置。

    2. PG和PGTH的电压如何正确理解?其中PGTH上升电压(1.2V)是否和UVLO的上升电压(1.2V)原理一致? 

    关于这个问题,请参考上图,他们内部都存在一个比较器的逻辑,所以说它们是相似的,但是不同的是都受到外界影响所以又存在一定出入。

    3.如果问题1中,PG和PGTH为必选,如何配合电压进行电阻的匹配?如输出3.3V。

    请看1中的解释说明,这个信号更多是来衡量IC的工作状态以及是否处于被设置的范围中。关于您对于这个的匹配问题,这是官方的计算器,您可以参考这个里面的参数建议。

    https://www.ti.com.cn/tool/cn/download/SLVRBL4

    4.正常工作时,PG和PGTH应为高电平,但实际测试评估板均为低电平,但输出电压正常。该现象是否正常?如实际应用中有无影响?

    首先您给的那个图是一个时序图,表示从初始信号开始按照某种时序依次变换,但是不表示在持续工作状态的情况。其次PGTH是输入,PG是输出他们的变化基础取决于状态。最后关于这个变化过程,请参考datasheet第20页 7.3.7 Power-Good Indication (PG)有详细说明。

    4.1 测试评估板时,欠压和过压电压已配置成功并验证可行,输出电压正常(VIN 3.3V)。PG上拉至VIN(J13 为23连接),PGTH上拉至Vout(J2为12连接)。此时测量PG电压0V,PGTH电压0.35V(1.该0.35V是否可理解为3.3V的电阻分压?理论计算电阻分压为0.35V;2.如为电阻分压,同时更改R12为40K,R13为27K,根据分压PGTH应为1.2V,但实际0V)

    请参考下图不是简单的分压。

  • 根据最后的图显示,PGTH输入电压至芯片与1.2V进行比较,PGTH外接的两个电阻为分压电阻。所以有以下问题:

    1.实际测试评估板中,Vout=3.3V,更改R12为40K,R13为27K,理论计算分压PGTH应为1.2V,但实际测出来PGTH电压为0V,PG电压0V。

    2. 此时接入1Ω负载,理论电流应为3.3A,但实际电流仅0.23A。是否有其他元件会影响Vout或Iout? 

  • 您好

    https://www.ti.com.cn/tool/cn/download/SLVRBL4

    您可以参考官方辅助设计工具来匹配满足您的需求。

  • 根据辅助工具配置PGset,和实际配置的电阻保持一致。此时Vout 3.3V正常输出,但PGTH电压为0V,PG电压0V。且此时接入1Ω负载,理论电流应为3.3A,但实际电流仅0.23A。

  • 您好

    根据您的说明PGTH 0V,根据datasheet的定义这个管脚是模拟输入。也就是说没有相关电压输入,也就是内部跟1.2V的比较应该是表示非正常状态。您PG是0V。因为这是输出管脚,根据内部逻辑,PG趋近于地。所以我建议您调整一下相关电路使得处于正常状态。详细操作请参考原文部分:The TPS22811x provides an active high digital output (PG) which serves as a power-good indication signal and is asserted high depending on the voltage at the PGTH pin along with the device state information. The PG is an open-drain pin and must be pulled up to an external supply. After power up, PG is pulled low initially. The device initiates a inrush sequence in which the HFET is turned on in a controlled manner. When the HFET gate voltage reaches the full overdrive indicating that the inrush sequence is complete and the voltage at PGTH is above VPGTH(R), the PG is asserted after a de-glitch time (tPGA). PG is de-asserted if at any time during normal operation, the voltage at PGTH falls below VPGTH(F), or the device detects a fault (except overcurrent). The PG de-assertion de-glitch time is tPGD。