Other Parts Discussed in Thread: OMAP-L138
尊敬的TI技术支持：
如标题，同样的电路板，非加密的能正常bootload，加密的dsp启动不正常。
1、从规格书上加密和非加密的C6748外围电路应该是共用的，请问，这2种芯片的外围电路是共用的吗？
2、对于加密C6748，我已经解锁JTAG，并可以用JTAG烧入Flash_Write.out把AIS文件下载到Norflash。
[C674X_0] Starting NORWriter.
[C674X_0] Enter the binary AIS application file name (enter 'none' to skip):
D:\Work2025\C6748_Codesecurity\delta_security_test\IMAGE\LED.bin
[C674X_0] File Loading Start
[C674X_0] File Load Finished.
[C674X_0] Erase Finished.
[C674X_0] Passed! (12180 bytes)
3、断开JTAG后，bootload拨码00000010，从NofFlash启动，但是dsp无法启动。我怀疑是out文件由SecureHexAIS_OMAP-L138生成AIS时，出错了。SecureHexAIS_OMAP-L138需要ini配置文件，我不知道我的ini对不对，下面是ini，麻烦帮我看看哪里出错了
; General settings that can be overwritten in the host code
; that calls the AISGen library.
[General]
; Can be 8 or 16 - used in emifa
busWidth=16
; SPIMASTER,I2CMASTER,EMIFA,NAND,EMAC,UART,PCI,HPI,USB,MMC_SD,VLYNQ,RAW
BootMode=EMIFA
;none
; 8,16,24 - used for SPI,I2C
;AddrWidth=8
; NO_CRC,SECTION_CRC,SINGLE_CRC
crcCheckType=NO_CRC
; TRUE/ON or FALSE/OFF
seqReadEn=ON
; Specify the symbol name for the boot finalize function
;FinalFxnSymbolName=none
; Security settings (keys, options, list of sections to encrypt, etc.)
[Security]
; Security Type: GENERIC, CUSTOM, NONE
securityType=GENERIC
; Boot Exit Type: NONSECURE, SECUREWITHSK, SECURENOSK
; NONSECURE = Device switches from secure type to non-secure type, jumping to loaded code
; (no secure kernel since no longer secure device).
; SECUREWITHSK = Device remains as secure type, secure kernel is loaded, allowing run-time
; security context switching.
bootExitType = NONSECURE
; Option to include in the generated key header the flag to force the JTAG off
;genericJTAGForceOff=FALSE
; Encrypt section list (ALL or comma-separated list of section names)
encryptSections=ALL
; CEK used for AES encryption of data - must be string of 32 hexadecimal characters
;encryptionKey=4A7E1F56AE545D487C452388A65B0C05
encryptionKey=efcdab89674523011032547698cadbfe
;encryptionKey=FA2E2CCC82EB537F0E8A7503C454525A
; Debug key
;keyEncryptionKey=0B94A91D33E597097F6C426F8F016872
;keyEncryptionKey=FA2E2CCC82EB537F0E8A7503C454525A
; SHA Algorithm Selection
genericSHASelection = SHA256
; Binary file containing secure key header for generic device
;genKeyHeaderFileName=../INI/ECEK.bin
; This section allows setting the PLL0 system clock with a
; specified multiplier and divider as shown. The clock source
; can also be chosen for internal or external.
; |------24|------16|-------8|-------0|
; PLL0CFG0: | CLKMODE| PLLM | PREDIV | POSTDIV|
; PLL0CFG1: | RSVD | PLLDIV1| PLLDIV3| PLLDIV7|
;
;PLL0 init for Core:456MHz, EMIFA:114MHz
;CPU_CLK = OSCIN（24MHz）÷（PREDIV+1）×（PLLM+1）÷（POSTDIV+1）
; = 24MHz ÷ (0+1) × (18 + 1) ÷ (0 + 1) = 456MHz
[PLL0CONFIG]
;PLL0CFG0 = 0x010F0000
PLL0CFG0 = 0x000F0000
PLL0CFG1 = 0x00000507
; This section allows setting up the PLL1. Usually this will
; take place as part of the EMIF3a DDR setup. The format of
; the input args is as follows:
; |------24|------16|-------8|-------0|
; PLL1CFG0: | PLLM| POSTDIV| PLLDIV1| PLLDIV2|
; PLL1CFG1: | RSVD | PLLDIV3|
;[PLL1CONFIG]
;PLL1CFG0 = 0x00000000
;PLL1CFG1 = 0x00000000
; This section lets us configure the peripheral interface
; of the current booting peripheral (I2C, SPI, or UART).
; Use with caution. The format of the PERIPHCLKCFG field
; is as follows:
; SPI: |------24|------16|-------8|-------0|
; | RSVD |PRESCALE|
;
; I2C: |------24|------16|-------8|-------0|
; | RSVD |PRESCALE| CLKL | CLKH |
;
; UART: |------24|------16|-------8|-------0|
; | RSVD | OSR | DLH | DLL |
; [PERIPHCLKCFG]
; PERIPHCLKCFG = 0x00010098
; This section allow setting the MPU1 or MPU2. If the
; rangenum is out of the allowed range then all the ranges
; (including the fixed range) take the start, end, and
; protection values.
; |------24|------16|----------8|----------0|
; MPUSELECT: | RSVD | mpuNum | rangeNum |
; STARTADDR: | startAddr |
; ENDADDR: | endAddr |
; MPPAVALUE: | mppaValue |
[MPUCONFIG]
MPUSELECT = 0x000001FF
STARTADDR = 0x00000000
ENDADDR = 0xFFFFFFFF
MPPAVALUE = 0xFFFFFFFF
; This section can be used to configure the PLL1 and the EMIF3a registers
; for starting the DDR2 interface.
; See PLL1CONFIG section for the format of the PLL1CFG fields.
; |------24|------16|-------8|-------0|
; PLL1CFG0: | PLL1CFG |
; PLL1CFG1: | PLL1CFG |
; DDRPHYC1R: | DDRPHYC1R |
; SDCR: | SDCR |
; SDTIMR: | SDTIMR |
; SDTIMR2: | SDTIMR2 |
; SDRCR: | SDRCR |
; CLK2XSRC: | CLK2XSRC |
;
;PLL1 init for DDR:156MHz
;[EMIF3DDR]
;PLL1CFG0 = 0x0D000001
;PLL1CFG1 = 0x00000002
;DDRPHYC1R = 0x000000C3
;SDCR = 0x00134632
;SDTIMR = 0x264A2A09
;SDTIMR2 = 0x4412C722
;SDRCR = 0x40000260
;CLK2XSRC = 0x00000000
; This section allow setting the MPU1 or MPU2. If the
; rangenum is out of the allowed range then all the ranges
; (including the fixed range) take the start, end, and
; protection values.
; |------24|------16|----------8|----------0|
; MPUSELECT: | RSVD | mpuNum | rangeNum |
; STARTADDR: | startAddr |
; ENDADDR: | endAddr |
; MPPAVALUE: | mppaValue |
;
; This MPU control must happen after the DDR init or else the
; MPU control has no effect
[MPUCONFIG]
MPUSELECT = 0x000002FF
STARTADDR = 0x00000000
ENDADDR = 0xFFFFFFFF
MPPAVALUE = 0xFFFFFFFF
; This section can be used to configure the EMIFA to use
; CS0 as an SDRAM interface. The fields required to do this
; are given below.
; |------24|------16|-------8|-------0|
; SDBCR: | SDBCR |
; SDTIMR: | SDTIMR |
; SDRSRPDEXIT: | SDRSRPDEXIT |
; SDRCR: | SDRCR |
; DIV4p5_CLK_ENABLE: | DIV4p5_CLK_ENABLE |
[EMIF25SDRAM]
SDBCR = 0x00004721
SDTIMR = 0x21113410
SDRSRPDEXIT = 0x00000006
SDRCR = 0x0000020D
DIV4p5_CLK_ENABLE = 0x00000000
; This section can be used to configure the async chip selects
; of the EMIFA (CS2-CS5). The fields required to do this
; are given below.
; |------24|------16|-------8|-------0|
; A1CR: | A1CR |
; A2CR: | A2CR |
; A3CR: | A3CR |
; A4CR: | A4CR |
; NANDFCR: | NANDFCR |
[EMIF25ASYNC]
A1CR = 0x0C42639D
A2CR = 0x104222DD
A3CR = 0x14DAA6FD
A4CR = 0x0932499D
NANDFCR = 0x00000012
; This section should be used in place of PLL0CONFIG when
; the I2C, SPI, or UART modes are being used. This ensures that
; the system PLL and the peripheral's clocks are changed together.
; See PLL0CONFIG section for the format of the PLL0CFG fields.
; See PERIPHCLKCFG section for the format of the CLKCFG field.
; |------24|------16|-------8|-------0|
; PLL0CFG0: | PLL0CFG |
; PLL0CFG1: | PLL0CFG |
; PERIPHCLKCFG: | CLKCFG |
; 如果想从串口启动的话需要这样配置，否则“GenericSecureUartHost.exe”工具
; 会出现“操作已超时”，无法下载成功。
; 这几句的作用是把CPU时钟配置为456MHz
; UART波特率配置为115200
; Divisor= (CPU_CLK/2)/(baud_rate*16); [OSR = 0]
; Divisor= (CPU_CLK/2)/(baud_rate*13); [OSR = 1]
[PLLANDCLOCKCONFIG]
PLL0CFG0 = 0x000F0000
PLL0CFG1 = 0x00000507
PERIPHCLKCFG = 0x00010085
; This section should be used to setup the power state of modules
; of the two PSCs. This section can be included multiple times to
; allow the configuration of any or all of the device modules.
; |------24|------16|-------8|-------0|
; LPSCCFG: | PSCNUM | MODULE | PD | STATE |
;PSC0
[PSCCONFIG]
LPSCCFG=0x00000003
;LPSC_EDMA_CC0
[PSCCONFIG]
LPSCCFG=0x00010003
;LPSC_EDMA_TC0
[PSCCONFIG]
LPSCCFG=0x00020003
;LPSC_EDMA_TC1
[PSCCONFIG]
LPSCCFG=0x00030003
;LPSC_EMIFA
[PSCCONFIG]
LPSCCFG=0x00040003
;LPSC_SPI0
;[PSCCONFIG]
;LPSCCFG=0x00050003
;LPSC_MMC/SD0
;6-8 not used
[PSCCONFIG]
LPSCCFG=0x00090003
;LPSC_UART0
;10 not used
;[PSCCONFIG]
;LPSCCFG=0x000B0003
;LPSC_SCR1
;[PSCCONFIG]
;LPSCCFG=0x000C0003
;LPSC_SCR2
;使能后程序不能正常加载
; [PSCCONFIG]
; LPSCCFG=0x000D0003
;LPSC_PRU
;14 not used
[PSCCONFIG]
LPSCCFG=0x000F0103
;LPSC_DSP
;PSC1
[PSCCONFIG]
LPSCCFG=0x01000003
;LPSC_EDMA_CC1
;[PSCCONFIG]
;LPSCCFG=0x01010003
;LPSC_USB20
;[PSCCONFIG]
;LPSCCFG=0x01020003
;LPSC_USB11
[PSCCONFIG]
LPSCCFG=0x01030003
;LPSC_GPIO
;[PSCCONFIG]
;LPSCCFG=0x01040003
;LPSC_UHPI
[PSCCONFIG]
LPSCCFG=0x01050003
;LPSC_EMAC
;[PSCCONFIG]
;LPSCCFG=0x01060003
;LPSC_DDR
;[PSCCONFIG]
;LPSCCFG=0x01070003
;LPSC_MCASP0
; 这里打开SATA的PSC后GenericSecureUartHost.exe程序不能正常加载到DSP
;[PSCCONFIG]
;LPSCCFG=0x01080003
;LPSC_SATA
;[PSCCONFIG]
;LPSCCFG=0x01090003
;LPSC_VPIF
[PSCCONFIG]
LPSCCFG=0x010A0003
;LPSC_SPI1
;[PSCCONFIG]
;LPSCCFG=0x010B0003
;LPSC_I2C1
[PSCCONFIG]
LPSCCFG=0x010C0003
;LPSC_UART1
[PSCCONFIG]
LPSCCFG=0x010D0003
;LPSC_UART2
;[PSCCONFIG]
;LPSCCFG=0x010E0003
;LPSC_MCBSP0
;[PSCCONFIG]
;LPSCCFG=0x010F0003
;LPSC_MCBSP1
;[PSCCONFIG]
;LPSCCFG=0x01100003
;LPSC_LCDC
;[PSCCONFIG]
;LPSCCFG=0x01110003
;LPSC_EPWM
;[PSCCONFIG]
;LPSCCFG=0x01120003
;LPSC_MMCSD1
;[PSCCONFIG]
;LPSCCFG=0x01130003
;LPSC_UPP
[PSCCONFIG]
LPSCCFG=0x01140003
;LPSC_ECAP
[PSCCONFIG]
LPSCCFG=0x01150003
;LPSC_EDMA_TC2
;22-23 not used
;[PSCCONFIG]
;LPSCCFG=0x01180003
;LPSC_SCR_F0
;[PSCCONFIG]
;LPSCCFG=0x01190003
;LPSC_SCR_F1
;[PSCCONFIG]
;LPSCCFG=0x011A0003
;LPSC_SCR_F2
;[PSCCONFIG]
;LPSCCFG=0x011B0003
;LPSC_SCR_F6
;[PSCCONFIG]
;LPSCCFG=0x011C0003
;LPSC_SCR_F7
;[PSCCONFIG]
;LPSCCFG=0x011D0003
;LPSC_SCR_F8
;[PSCCONFIG]
;LPSCCFG=0x011E0003
;LPSC_BR_F7
[PSCCONFIG]
LPSCCFG=0x011F0103
;LPSC_SHARED_RAM
; This section allows setting of a single PINMUX register.
; This section can be included multiple times to allow setting
; as many PINMUX registers as needed.
; |------24|------16|-------8|-------0|
; REGNUM: | regNum |
; MASK: | mask |
; VALUE: | value |
;[PINMUX]
;REGNUM = 4
;MASK = 0x00FF0000
;VALUE = 0x00220000
;[PINMUX]
;REGNUM = 5
;MASK = 0xFF00000F
;VALUE = 0x11000008
;[PINMUX]
;REGNUM = 6
;MASK = 0xFFFFFFFF
;VALUE = 0x11111111
;[PINMUX]
;REGNUM = 7
;MASK = 0xFFFFFFFF
;VALUE = 0x18111111
;[PINMUX]
;REGNUM = 8
;MASK = 0xFFFFFFFF
;VALUE = 0x11111111
;[PINMUX]
;REGNUM = 9
;MASK = 0xFFFFFFFF
;VALUE = 0x11111111
;[PINMUX]
;REGNUM = 10
;MASK = 0xFFFFFFFF
;VALUE = 0x11111118
;[PINMUX]
;REGNUM = 11
;MASK = 0xFFFFFFFF
;VALUE = 0x11111111
;[PINMUX]
;REGNUM = 12
;MASK = 0xFFFFFFFF
;VALUE = 0x11111111
; No Params required - simply include this section for the fast boot function to be called
;[FASTBOOT]
; This section allows configuration of one the systme IOPUs.
; The iopuNum field must be valid (0-5) and then mppaStart
; and mppaend fields allow setting a range of mppa MMRs to the
; same supplied mppa value.
; IOPUSELECT: | RSVD | iopuNum| mppaStart | mppaEnd |
; MPPAVALUE: | mppaValue |
[IOPUCONFIG]
IOPUSELECT = 0x000000FF
MPPAVALUE = 0xFFFFFFFF
[IOPUCONFIG]
IOPUSELECT = 0x000100FF
MPPAVALUE = 0xFFFFFFFF
[IOPUCONFIG]
IOPUSELECT = 0x000200FF
MPPAVALUE = 0xFFFFFFFF
[IOPUCONFIG]
IOPUSELECT = 0x000300FF
MPPAVALUE = 0xFFFFFFFF
; (ZZY) IOPU4为自行添加
;[IOPUCONFIG]
;IOPUSELECT = 0x000400FF
;MPPAVALUE = 0xFFFFFFFF
;[IOPUCONFIG]
;IOPUSELECT = 0x000500FF
;MPPAVALUE = 0xFFFFFFFF
; (ZZY) 来自E2E技术支持(Rahul Prabhu)回复内容
; 这将设置IOPU6寄存器中所有安全位以解锁所有受保护IO的安全保护，但将锁定SYSCFG寄存器以仅由安全主管ROM或安全内核方位。
[IOPUCONFIG]
IOPUSELECT = 0x000600FF
MPPAVALUE = 0xFFFFFFFF
; (ZZY) 来自E2E技术支持(Rahul Prabhu)回复内容
; (ZZY) 这会将IOPU6的第7位设置为0，这将解锁SYSCFG寄存器上的安全保护，理想情况下这是配置PINMUX和其它系统寄存器所需的。
[IOPUCONFIG]
IOPUSELECT = 0x00060707
MPPAVALUE = 0x00000000
; This section allow setting the MPU1 or MPU2. If the
; rangenum is out of the allowed range then all the ranges
; (including the fixed range) take the start, end, and
; protection values.
; |------24|------16|----------8|----------0|
; MPUSELECT: | RSVD | mpuNum | rangeNum |
; STARTADDR: | startAddr |
; ENDADDR: | endAddr |
; MPPAVALUE: | mppaValue |
;[MPUCONFIG]
;MPUSELECT = 0x000001FF
;STARTADDR = 0x00000000
;ENDADDR = 0x00000000
;MPPAVALUE = 0xFFFFFFFF
; This function allows the user to selectively open up the
; the debug TAPs of the device. Since the function is not
; executed until the signature is checked, it does not
; pose a security issue.
; |------24|------16|----------8|----------0|
; TAPSCFG: | RSVD | tapscfg |
[TAPSCONFIG]
;TAPSCFG = 0x00000000
TAPSCFG = 0x0000FFFF
