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"> Shared Level 3 memory—The MSMC memory is not directly cacheable at the C66x L2, but is cacheable in C66x L1D and L1P. However, if it is remapped to an external address using the address-extension capabilities in the C66x CorePac MPAX, the MSMC memory can be cached as a shared L3 memory both in the L1 and L2 caches of C66x CorePac. To achieve this, the caching must be enabled in MAR registers (using MAR.PC bit) for the remapped region.
