我使用的是AM3517 CPU， GPMC的CS3 上挂了CPLD器件，使用同步方式16bit NOR-Like device访问.
我配置了地址线寄存器，数据线寄存器，CS线寄存器，nADV_ALE, nOE, nWE, gpmc_clk
然后配置GPMC的寄存器。
现在遇到了这样的问题：
1. 读取数据时，从示波器上看，只GPMC_CLK线上只发送了一次clock，数据被正确读出，然后就再也不发clock了，是什么原因呢？
如下是我的配置代码，哪里有问题吗？
#define NAND_PADCONF_SDRC_DQS3_CLR 0x0000FFFF
#define NAND_PADCONF_SDRC_DQS3_EN (AM3X_CTRL_PADCONF_INPUT_DIS1 | \
AM3X_CTRL_PADCONF_PULLTYPE_DOWN1 | \
AM3X_CTRL_PADCONF_PULLTYPE_DIS1 | \
AM3X_CTRL_PADCONF_MODE0_1)
#define NAND_PADCONF_GPMC_A2_EN (AM3X_CTRL_PADCONF_INPUT_DIS0 | \
AM3X_CTRL_PADCONF_PULLTYPE_DOWN0 | \
AM3X_CTRL_PADCONF_PULLTYPE_EN0 | \
AM3X_CTRL_PADCONF_MODE0_0 | \
AM3X_CTRL_PADCONF_INPUT_DIS1 | \
AM3X_CTRL_PADCONF_PULLTYPE_DOWN1 | \
AM3X_CTRL_PADCONF_PULLTYPE_EN1 | \
AM3X_CTRL_PADCONF_MODE0_1)
#define NAND_PADCONF_GPMC_A4_EN (AM3X_CTRL_PADCONF_INPUT_DIS0 | \
AM3X_CTRL_PADCONF_PULLTYPE_DOWN0 | \
AM3X_CTRL_PADCONF_PULLTYPE_EN0 | \
AM3X_CTRL_PADCONF_MODE0_0 | \
AM3X_CTRL_PADCONF_INPUT_DIS1 | \
AM3X_CTRL_PADCONF_PULLTYPE_DOWN1 | \
AM3X_CTRL_PADCONF_PULLTYPE_EN1 | \
AM3X_CTRL_PADCONF_MODE0_1)
#define NAND_PADCONF_GPMC_A6_EN (AM3X_CTRL_PADCONF_INPUT_DIS0 | \
AM3X_CTRL_PADCONF_PULLTYPE_DOWN0 | \
AM3X_CTRL_PADCONF_PULLTYPE_EN0 | \
AM3X_CTRL_PADCONF_MODE0_0 | \
AM3X_CTRL_PADCONF_INPUT_DIS1 | \
AM3X_CTRL_PADCONF_PULLTYPE_DOWN1 | \
AM3X_CTRL_PADCONF_PULLTYPE_EN1 | \
AM3X_CTRL_PADCONF_MODE0_1)
#define NAND_PADCONF_GPMC_A8_EN (AM3X_CTRL_PADCONF_INPUT_DIS0 | \
AM3X_CTRL_PADCONF_PULLTYPE_DOWN0 | \
AM3X_CTRL_PADCONF_PULLTYPE_EN0 | \
AM3X_CTRL_PADCONF_MODE0_0 | \
AM3X_CTRL_PADCONF_INPUT_DIS1 | \
AM3X_CTRL_PADCONF_PULLTYPE_DOWN1 | \
AM3X_CTRL_PADCONF_PULLTYPE_EN1 | \
AM3X_CTRL_PADCONF_MODE0_1)
#define NAND_PADCONF_GPMC_A10_EN (AM3X_CTRL_PADCONF_INPUT_DIS0 | \
AM3X_CTRL_PADCONF_PULLTYPE_DOWN0 | \
AM3X_CTRL_PADCONF_PULLTYPE_EN0 | \
AM3X_CTRL_PADCONF_MODE0_0 | \
AM3X_CTRL_PADCONF_INPUT_EN1 | \
AM3X_CTRL_PADCONF_PULLTYPE_UP1 | \
AM3X_CTRL_PADCONF_PULLTYPE_EN1 | \
AM3X_CTRL_PADCONF_MODE0_1)
#define NAND_PADCONF_GPMC_D1_EN (AM3X_CTRL_PADCONF_INPUT_EN0 | \
AM3X_CTRL_PADCONF_PULLTYPE_UP0 | \
AM3X_CTRL_PADCONF_PULLTYPE_EN0 | \
AM3X_CTRL_PADCONF_MODE0_0 | \
AM3X_CTRL_PADCONF_INPUT_EN1 | \
AM3X_CTRL_PADCONF_PULLTYPE_UP1 | \
AM3X_CTRL_PADCONF_PULLTYPE_EN1 | \
AM3X_CTRL_PADCONF_MODE0_1)
#define NAND_PADCONF_GPMC_D3_EN (AM3X_CTRL_PADCONF_INPUT_EN0 | \
AM3X_CTRL_PADCONF_PULLTYPE_UP0 | \
AM3X_CTRL_PADCONF_PULLTYPE_EN0 | \
AM3X_CTRL_PADCONF_MODE0_0 | \
AM3X_CTRL_PADCONF_INPUT_EN1 | \
AM3X_CTRL_PADCONF_PULLTYPE_UP1 | \
AM3X_CTRL_PADCONF_PULLTYPE_EN1 | \
AM3X_CTRL_PADCONF_MODE0_1)
#define NAND_PADCONF_GPMC_D5_EN (AM3X_CTRL_PADCONF_INPUT_EN0 | \
AM3X_CTRL_PADCONF_PULLTYPE_UP0 | \
AM3X_CTRL_PADCONF_PULLTYPE_EN0 | \
AM3X_CTRL_PADCONF_MODE0_0 | \
AM3X_CTRL_PADCONF_INPUT_EN1 | \
AM3X_CTRL_PADCONF_PULLTYPE_UP1 | \
AM3X_CTRL_PADCONF_PULLTYPE_EN1 | \
AM3X_CTRL_PADCONF_MODE0_1)
#define NAND_PADCONF_GPMC_D7_EN (AM3X_CTRL_PADCONF_INPUT_EN0 | \
AM3X_CTRL_PADCONF_PULLTYPE_UP0 | \
AM3X_CTRL_PADCONF_PULLTYPE_EN0 | \
AM3X_CTRL_PADCONF_MODE0_0 | \
AM3X_CTRL_PADCONF_INPUT_EN1 | \
AM3X_CTRL_PADCONF_PULLTYPE_UP1 | \
AM3X_CTRL_PADCONF_PULLTYPE_EN1 | \
AM3X_CTRL_PADCONF_MODE0_1)
#define NAND_PADCONF_GPMC_D9_EN (AM3X_CTRL_PADCONF_INPUT_EN0 | \
AM3X_CTRL_PADCONF_PULLTYPE_UP0 | \
AM3X_CTRL_PADCONF_PULLTYPE_EN0 | \
AM3X_CTRL_PADCONF_MODE0_0 | \
AM3X_CTRL_PADCONF_INPUT_EN1 | \
AM3X_CTRL_PADCONF_PULLTYPE_UP1 | \
AM3X_CTRL_PADCONF_PULLTYPE_EN1 | \
AM3X_CTRL_PADCONF_MODE0_1)
#define NAND_PADCONF_GPMC_D11_EN (AM3X_CTRL_PADCONF_INPUT_EN0 | \
AM3X_CTRL_PADCONF_PULLTYPE_UP0 | \
AM3X_CTRL_PADCONF_PULLTYPE_EN0 | \
AM3X_CTRL_PADCONF_MODE0_0 | \
AM3X_CTRL_PADCONF_INPUT_EN1 | \
AM3X_CTRL_PADCONF_PULLTYPE_UP1 | \
AM3X_CTRL_PADCONF_PULLTYPE_EN1 | \
AM3X_CTRL_PADCONF_MODE0_1)
#define NAND_PADCONF_GPMC_D13_EN (AM3X_CTRL_PADCONF_INPUT_EN0 | \
AM3X_CTRL_PADCONF_PULLTYPE_UP0 | \
AM3X_CTRL_PADCONF_PULLTYPE_EN0 | \
AM3X_CTRL_PADCONF_MODE0_0 | \
AM3X_CTRL_PADCONF_INPUT_EN1 | \
AM3X_CTRL_PADCONF_PULLTYPE_UP1 | \
AM3X_CTRL_PADCONF_PULLTYPE_EN1 | \
AM3X_CTRL_PADCONF_MODE0_1)
#define NAND_PADCONF_GPMC_D15_EN (AM3X_CTRL_PADCONF_INPUT_EN0 | \
AM3X_CTRL_PADCONF_PULLTYPE_UP0 | \
AM3X_CTRL_PADCONF_PULLTYPE_EN0 | \
AM3X_CTRL_PADCONF_MODE0_0 | \
AM3X_CTRL_PADCONF_INPUT_DIS1 | \
AM3X_CTRL_PADCONF_PULLTYPE_UP1 | \
AM3X_CTRL_PADCONF_PULLTYPE_EN1 | \
AM3X_CTRL_PADCONF_MODE0_1)
#define NAND_PADCONF_GPMC_NCS1_EN (AM3X_CTRL_PADCONF_INPUT_DIS0 | \
AM3X_CTRL_PADCONF_PULLTYPE_UP0 | \
AM3X_CTRL_PADCONF_PULLTYPE_EN0 | \
AM3X_CTRL_PADCONF_MODE0_0 | \
AM3X_CTRL_PADCONF_INPUT_DIS1 | \
AM3X_CTRL_PADCONF_PULLTYPE_UP1 | \
AM3X_CTRL_PADCONF_PULLTYPE_EN1 | \
AM3X_CTRL_PADCONF_MODE0_1)
#define NAND_PADCONF_GPMC_NCS3_EN (AM3X_CTRL_PADCONF_INPUT_DIS0 | \
AM3X_CTRL_PADCONF_PULLTYPE_UP0 | \
AM3X_CTRL_PADCONF_PULLTYPE_EN0 | \
AM3X_CTRL_PADCONF_MODE0_0 | \
AM3X_CTRL_PADCONF_INPUT_EN1 | \
AM3X_CTRL_PADCONF_PULLTYPE_UP1 | \
AM3X_CTRL_PADCONF_PULLTYPE_EN1 | \
AM3X_CTRL_PADCONF_MODE0_1)
#define NAND_PADCONF_GPMC_NCS5_EN (AM3X_CTRL_PADCONF_INPUT_DIS0 | \
AM3X_CTRL_PADCONF_PULLTYPE_UP0 | \
AM3X_CTRL_PADCONF_PULLTYPE_EN0 | \
AM3X_CTRL_PADCONF_MODE0_0 | \
AM3X_CTRL_PADCONF_INPUT_EN1 | \
AM3X_CTRL_PADCONF_PULLTYPE_DOWN1 | \
AM3X_CTRL_PADCONF_PULLTYPE_DIS1 | \
AM3X_CTRL_PADCONF_MODE0_1)
#define NAND_PADCONF_GPMC_NCS7_EN (AM3X_CTRL_PADCONF_INPUT_EN0 | \
AM3X_CTRL_PADCONF_PULLTYPE_UP0 | \
AM3X_CTRL_PADCONF_PULLTYPE_EN0 | \
AM3X_CTRL_PADCONF_MODE0_0 | \
AM3X_CTRL_PADCONF_INPUT_EN1 | \
AM3X_CTRL_PADCONF_PULLTYPE_UP1 | \
AM3X_CTRL_PADCONF_PULLTYPE_EN1 | \
AM3X_CTRL_PADCONF_MODE0_1)
#define NAND_PADCONF_GPMC_NADV_ALE_EN (AM3X_CTRL_PADCONF_INPUT_DIS0 | \
AM3X_CTRL_PADCONF_PULLTYPE_DOWN0 | \
AM3X_CTRL_PADCONF_PULLTYPE_DIS0 | \
AM3X_CTRL_PADCONF_MODE0_0 | \
AM3X_CTRL_PADCONF_INPUT_DIS1 | \
AM3X_CTRL_PADCONF_PULLTYPE_DOWN1 | \
AM3X_CTRL_PADCONF_PULLTYPE_DIS1 | \
AM3X_CTRL_PADCONF_MODE0_1)
#define NAND_PADCONF_GPMC_NWE_EN (AM3X_CTRL_PADCONF_INPUT_DIS0 | \
AM3X_CTRL_PADCONF_PULLTYPE_DOWN0 | \
AM3X_CTRL_PADCONF_PULLTYPE_DIS0 | \
AM3X_CTRL_PADCONF_MODE0_0 | \
AM3X_CTRL_PADCONF_INPUT_DIS1 | \
AM3X_CTRL_PADCONF_PULLTYPE_UP1 | \
AM3X_CTRL_PADCONF_PULLTYPE_EN1 | \
AM3X_CTRL_PADCONF_MODE0_1)
#define NAND_PADCONF_GPMC_NBE1_EN (AM3X_CTRL_PADCONF_INPUT_EN0 | \
AM3X_CTRL_PADCONF_PULLTYPE_UP0 | \
AM3X_CTRL_PADCONF_PULLTYPE_EN0 | \
AM3X_CTRL_PADCONF_MODE0_0 | \
AM3X_CTRL_PADCONF_INPUT_EN1 | \
AM3X_CTRL_PADCONF_PULLTYPE_DOWN1 | \
AM3X_CTRL_PADCONF_PULLTYPE_DIS1 | \
AM3X_CTRL_PADCONF_MODE0_1)
#define NAND_PADCONF_GPMC_WAIT0_EN (AM3X_CTRL_PADCONF_INPUT_EN0 | \
AM3X_CTRL_PADCONF_PULLTYPE_UP0 | \
AM3X_CTRL_PADCONF_PULLTYPE_EN0 | \
AM3X_CTRL_PADCONF_MODE0_0 | \
AM3X_CTRL_PADCONF_INPUT_EN1 | \
AM3X_CTRL_PADCONF_PULLTYPE_UP1 | \
AM3X_CTRL_PADCONF_PULLTYPE_EN1 | \
AM3X_CTRL_PADCONF_MODE0_1)
#define NAND_PADCONF_GPMC_WAIT2_EN (AM3X_CTRL_PADCONF_INPUT_EN0 | \
AM3X_CTRL_PADCONF_PULLTYPE_UP0 | \
AM3X_CTRL_PADCONF_PULLTYPE_EN0 | \
AM3X_CTRL_PADCONF_MODE0_0 | \
AM3X_CTRL_PADCONF_INPUT_EN1 | \
AM3X_CTRL_PADCONF_PULLTYPE_UP1 | \
AM3X_CTRL_PADCONF_PULLTYPE_EN1 | \
AM3X_CTRL_PADCONF_MODE0_1)
/* Setup SDRC_DQS3 register. */
reg32 = ESAL_GE_MEM_READ32(AM3X_CTRL_PADCONF_SDRC_DQS3);
reg32 &= NAND_PADCONF_SDRC_DQS3_CLR;
reg32 |= NAND_PADCONF_SDRC_DQS3_EN;
ESAL_GE_MEM_WRITE32(AM3X_CTRL_PADCONF_SDRC_DQS3, reg32);
/* Setup GPMC_A2 register. */
ESAL_GE_MEM_WRITE32(AM3X_CTRL_PADCONF_GPMC_A2, NAND_PADCONF_GPMC_A2_EN);
/* Setup GPMC_A4 register. */
ESAL_GE_MEM_WRITE32(AM3X_CTRL_PADCONF_GPMC_A4, NAND_PADCONF_GPMC_A4_EN);
/* Setup GPMC_A6 register. */
ESAL_GE_MEM_WRITE32(AM3X_CTRL_PADCONF_GPMC_A6, NAND_PADCONF_GPMC_A6_EN);
/* Setup GPMC_A8 register. */
ESAL_GE_MEM_WRITE32(AM3X_CTRL_PADCONF_GPMC_A8, NAND_PADCONF_GPMC_A8_EN);
/* Setup GPMC_A10 register. */
ESAL_GE_MEM_WRITE32(AM3X_CTRL_PADCONF_GPMC_A10, NAND_PADCONF_GPMC_A10_EN);
/* Setup GPMC_D1 register. */
ESAL_GE_MEM_WRITE32(AM3X_CTRL_PADCONF_GPMC_D1, NAND_PADCONF_GPMC_D1_EN);
/* Setup GPMC_D3 register. */
ESAL_GE_MEM_WRITE32(AM3X_CTRL_PADCONF_GPMC_D3, NAND_PADCONF_GPMC_D3_EN);
/* Setup GPMC_D5 register. */
ESAL_GE_MEM_WRITE32(AM3X_CTRL_PADCONF_GPMC_D5, NAND_PADCONF_GPMC_D5_EN);
/* Setup GPMC_D7 register. */
ESAL_GE_MEM_WRITE32(AM3X_CTRL_PADCONF_GPMC_D7, NAND_PADCONF_GPMC_D7_EN);
/* Setup GPMC_D9 register. */
ESAL_GE_MEM_WRITE32(AM3X_CTRL_PADCONF_GPMC_D9, NAND_PADCONF_GPMC_D9_EN);
/* Setup GPMC_D11 register. */
ESAL_GE_MEM_WRITE32(AM3X_CTRL_PADCONF_GPMC_D11, NAND_PADCONF_GPMC_D11_EN);
/* Setup GPMC_D13 register. */
ESAL_GE_MEM_WRITE32(AM3X_CTRL_PADCONF_GPMC_D13, NAND_PADCONF_GPMC_D13_EN);
/* Setup GPMC_D15 register. */
ESAL_GE_MEM_WRITE32(AM3X_CTRL_PADCONF_GPMC_D15, NAND_PADCONF_GPMC_D15_EN);
/* Setup GPMC_NCS1 register. */
ESAL_GE_MEM_WRITE32(AM3X_CTRL_PADCONF_GPMC_NCS1, NAND_PADCONF_GPMC_NCS1_EN);
/* Setup GPMC_NCS3 register. */
ESAL_GE_MEM_WRITE32(AM3X_CTRL_PADCONF_GPMC_NCS3, NAND_PADCONF_GPMC_NCS3_EN);
/* Setup GPMC_NCS5 register. */
ESAL_GE_MEM_WRITE32(AM3X_CTRL_PADCONF_GPMC_NCS5, NAND_PADCONF_GPMC_NCS5_EN);
/* Setup GPMC_NCS7 register. */
ESAL_GE_MEM_WRITE32(AM3X_CTRL_PADCONF_GPMC_NCS7, NAND_PADCONF_GPMC_NCS7_EN);
/* Setup GPMC_NADV_ALE register. */
ESAL_GE_MEM_WRITE32(AM3X_CTRL_PADCONF_GPMC_NADV_ALE, NAND_PADCONF_GPMC_NADV_ALE_EN);
/* Setup GPMC_NWE register. */
ESAL_GE_MEM_WRITE32(AM3X_CTRL_PADCONF_GPMC_NWE, NAND_PADCONF_GPMC_NWE_EN);
/* Setup GPMC_NBE1 register. */
ESAL_GE_MEM_WRITE32(AM3X_CTRL_PADCONF_GPMC_NBE1, NAND_PADCONF_GPMC_NBE1_EN);
/* Setup GPMC_WAIT0 register. */
ESAL_GE_MEM_WRITE32(AM3X_CTRL_PADCONF_GPMC_WAIT0, NAND_PADCONF_GPMC_WAIT0_EN);
/* Setup GPMC_WAIT2 register. */
ESAL_GE_MEM_WRITE32(AM3X_CTRL_PADCONF_GPMC_WAIT2, NAND_PADCONF_GPMC_WAIT2_EN);
/* Reset GPMC controller. */
ESAL_GE_MEM_WRITE32(AM3X_GPMC_SYSCONFIG, 0x00000002);
/* Wait till the reset clears. */
while (!(ESAL_GE_MEM_READ32(AM3X_GPMC_SYSSTATUS)));
/* Clear GPMC timeout control register. */
ESAL_GE_MEM_WRITE32(AM3X_GPMC_TIMEOUT_CTRL, 0);
/* Disable GPMC IRQ. */
ESAL_GE_MEM_WRITE32(AM3X_GPMC_IRQEN, 0);
/* Configure limited address device support. */
ESAL_GE_MEM_WRITE32(AM3X_GPMC_CONFIG, 0x00000002);
/**********************************************************/
/* CS3 -> CPLD 0x18000000 */
/**********************************************************/
/* GPMC_CONFIG1 */
/* Name bits data */
/* ---- ---- ---- */
/* wrapburst 31 0x00000000 */
/* readmultiple 30 0x00000000 */
/* readtype 29 0x00000000 */
/* writemultiple 28 0x00000000 */
/* writetype 27 0x00000000 */
/* clkactivationtime 25-26 0x00000000 */
/* attacheddevicepagelength 23-24 0x00000000 */
/* waitreadmonitoring 22 0x00000000 */
/* waitwritemonitoring 21 0x00000000 */
/* reserved 20 0x00000000 */
/* waitmonitoringtime 18-19 0x00000000 */
/* waitpinselect 16-17 0x00000000 */
/* reserved 14-15 0x00000000 */
/* devicesize 12-13 0x00001000 */
/* devicetype 10-11 0x00000000 */
/* muxadddata 9 0x00000000 */
/* reserved 5-8 0x00000000 */
/* timeparagranularity 4 0x00000000 */
/* reserved 2-3 0x00000000 */
/* gpmcfclkdivider 0-1 0x00000000 */
/* ---------- */
/* 0x00001000 */
/**********************************************************/
ESAL_GE_MEM_WRITE32(AM3X_GPMC_CONFIG1_3, 0x28001000);
/**********************************************************/
/* GPMC_CONFIG2 */
/* Name bits data */
/* ---- ---- ---- */
/* reserved 21-31 0x00000000 */
/* cswrofftime 16-20 0x00080000 */
/* reserved 13-15 0x00000000 */
/* csrdofftime 8-12 0x00000800 */
/* csextradelay 7 0x00000000 */
/* reserved 4-6 0x00000000 */
/* csontime 0-3 0x00000000 */
/* ---------- */
/* 0x00080800 */
/**********************************************************/
//ESAL_GE_MEM_WRITE32(AM3X_GPMC_CONFIG2_3, 0x001e1e01);
/**********************************************************/
/* GPMC_CONFIG3 */
/* Name bits data */
/* ---- ---- ---- */
/* reserved 21-31 0x00000000 */
/* advwrofftime 16-20 0x00080000 */
/* reserved 13-15 0x00000000 */
/* advrdofftime 8-12 0x00000800 */
/* advextradelay 7 0x00000000 */
/* reserved 4-6 0x00000000 */
/* advontime 0-3 0x00000000 */
/* ---------- */
/* 0x00080800 */
/**********************************************************/
//ESAL_GE_MEM_WRITE32(AM3X_GPMC_CONFIG3_3, 0x00080300);
/**********************************************************/
/* GPMC_CONFIG4 */
/* Name bits data */
/* ---- ---- ---- */
/* reserved 29-31 0x00000000 */
/* weofftime 24-28 0x06000000 */
/* weextradelay 23 0x00000000 */
/* reserved 20-22 0x00000000 */
/* weontime 16-19 0x00000000 */
/* reserved 13-15 0x00000000 */
/* oeofftime 8-12 0x00000600 */
/* oeextradelay 7 0x00000000 */
/* reserved 4-6 0x00000000 */
/* oeontime 0-3 0x00000000 */
/* ---------- */
/* 0x06000600 */
/**********************************************************/
//ESAL_GE_MEM_WRITE32(AM3X_GPMC_CONFIG4_3, 0x1c091c09);
/**********************************************************/
/* GPMC_CONFIG5 */
/* Name bits data */
/* ---- ---- ---- */
/* reserved 28-31 0x00000000 */
/* pageburstaccesstime 24-27 0x00000000 */
/* reserved 21-23 0x00000000 */
/* rdaccesstime 16-20 0x00080000 */
/* reserved 13-15 0x00000000 */
/* wrcycletime 8-12 0x00000800 */
/* reserved 5-7 0x00000000 */
/* rdcycletime 0-4 0x00000008 */
/* ---------- */
/* 0x00080808 */
/**********************************************************/
//ESAL_GE_MEM_WRITE32(AM3X_GPMC_CONFIG5_3, 0x00181f1f);
/**********************************************************/
/* GPMC_CONFIG6 */
/* Name bits data */
/* ---- ---- ---- */
/* reserved 29-31 0x00000000 */
/* wraccesstime 24-28 0x00000000 */
/* reserved 20-23 0x00000000 */
/* wrdataonadmuxbus 16-19 0x00000000 */
/* reserved 12-15 0x00000000 */
/* cycle2cycledelay 8-11 0x00000300 */
/* cycle2cyclesamecsen 7 0x00000080 */
/* cycle2cyclediffcsen 6 0x00000040 */
/* reserved 4-5 0x00000000 */
/* busturnaround 0-3 0x0000000F */
/* ---------- */
/* 0x000003CF */
/**********************************************************/
//ESAL_GE_MEM_WRITE32(AM3X_GPMC_CONFIG6_3, 0x00000FCF);
/**********************************************************/
/* GPMC_CONFIG7 */
/* Name bits data */
/* ---- ---- ---- */
/* reserved 12-31 0x00000000 */
/* maskaddress 8-11 0x00000F00 */
/* reserved 7 0x00000000 */
/* csvalid 6 0x00000040 */
/* baseaddress 0-5 0x00000018 */
/* ---------- */
/* 0x00000F58 */
/**********************************************************/
ESAL_GE_MEM_WRITE32(AM3X_GPMC_CONFIG7_3, 0x00000F58);
/* ================= CS4 SRAM Test ================= */
ESAL_GE_MEM_WRITE32(AM3X_GPMC_CONFIG1_4, 0x28001203);
//ESAL_GE_MEM_WRITE32(AM3X_GPMC_CONFIG2_4, 0x00000000);
//ESAL_GE_MEM_WRITE32(AM3X_GPMC_CONFIG3_4, 0x00000000);
//ESAL_GE_MEM_WRITE32(AM3X_GPMC_CONFIG4_4, 0x00000000);
//ESAL_GE_MEM_WRITE32(AM3X_GPMC_CONFIG5_4, 0x00000000);
//ESAL_GE_MEM_WRITE32(AM3X_GPMC_CONFIG6_4, 0x00000000);
/* base add: 0x20000000, 16MB */
ESAL_GE_MEM_WRITE32(AM3X_GPMC_CONFIG7_4, 0x00000F60);
/* ================================================= */
/* Disable write protect. */
ESAL_GE_MEM_WRITE32(AM3X_GPMC_CONFIG, 0x00000010);
/* Enable GPMC controller. */
ESAL_GE_MEM_WRITE32(AM3X_GPMC_SYSCONFIG, 0x00000008);
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