AM6442: Error when M4 accss DDR using RAT

Sherry gao

Part Number: AM6442

Hi Ti Experts,

I want to access the DDR space with the actual address 0xc0000000 in the M4 core.

I import hello_world_am64x-evm_m4fss0-0_freertos_ti-arm-clang example and modify the following content in the syscfg file:

I've change REGION2's system address from 0x40000000 to 0xc0000000. And I thought this modification could directly access 0xc0000000.

addr_translate1.$name     = "CONFIG_ADDR_TRANSLATE_REGION0";
addr_translate1.localAddr = 0x80000000;
addr_translate1.size      = 28;

addr_translate2.$name      = "CONFIG_ADDR_TRANSLATE_REGION1";
addr_translate2.systemAddr = 0x20000000;
addr_translate2.localAddr  = 0xA0000000;

addr_translate3.$name      = "CONFIG_ADDR_TRANSLATE_REGION2";
addr_translate3.systemAddr = 0xC0000000;
addr_translate3.localAddr  = 0xC0000000;

addr_translate4.$name      = "CONFIG_ADDR_TRANSLATE_REGION3";
addr_translate4.systemAddr = 0x60000000;
addr_translate4.localAddr  = 0x60000000;

addr_translate5.$name      = "CONFIG_ADDR_TRANSLATE_REGION4";
addr_translate5.size       = 28;
addr_translate5.localAddr  = 0x90000000;
addr_translate5.systemAddr = 0x80000000;

However, I meet Hwip_hardFault_handler () by this way.

Is there any way to access this DDR address(0xc0000000) in the M4 core?

Thanks,

xue

2 个月前

0 Alice 2 个月前

TI__Mastermind 35760 points

您好，
已经收到了您的案例，调查需要些时间，感谢您的耐心等待。

0 Links 2 个月前

TI__Mastermind 30320 points

You have to setup the RAT appropriately. Please check the GEL files associated with AM64x Code Composer. These have examples of how to setup the RAT so the M4 can have access to the DDR. See function below:

hotmenu Configure_RAT(){
//Configure RAT
// Available M3 space to remap =2GB, 0x6000_0000 - 0xDFFF_FFFF
// Configure the RAT for view into the SoC
// enable and set region size for first two regions

// region 0 0x60000000 - 0x80000000 -> 0x40000000 - 0x60000000
*(unsigned int *)(CSL_WKUP_DMSC0_RAT_BASE + 0x24) = 0x60000000; //If the M3 reads from here -------> IN ADDRESS
*(unsigned int *)(CSL_WKUP_DMSC0_RAT_BASE + 0x2C) = 0x00000000; //retrieve data from here -------> OUT ADDRESS[47:32] in RAT register[15:0]
*(unsigned int *)(CSL_WKUP_DMSC0_RAT_BASE + 0x28) = 0x40000000; // -------> OUT ADDRESS[31:0]
*(unsigned int *)(CSL_WKUP_DMSC0_RAT_BASE + 0x20) = 0x8000001D; //Size = 512MB and enable region

// region 1 0x80000000 - 0xA0000000 -> 0X0 - 0x20000000
*(unsigned int *)(CSL_WKUP_DMSC0_RAT_BASE + 0x34) = 0x80000000; //If the M3 reads from here -------> IN ADDRESS
*(unsigned int *)(CSL_WKUP_DMSC0_RAT_BASE + 0x3C) = 0x00000000; //retrieve data from here -------> OUT ADDRESS[47:32] in RAT register[15:0]
*(unsigned int *)(CSL_WKUP_DMSC0_RAT_BASE + 0x38) = 0x00000000; // -------> OUT ADDRESS[31:0]
*(unsigned int *)(CSL_WKUP_DMSC0_RAT_BASE + 0x30) = 0x8000001D; //Size = 512MB and enable region

//Disable region 2-15
*(unsigned int *)(CSL_WKUP_DMSC0_RAT_BASE + 0x40) = 0x00000000; //Region 2 Disable
*(unsigned int *)(CSL_WKUP_DMSC0_RAT_BASE + 0x50) = 0x00000000; //Region 3
*(unsigned int *)(CSL_WKUP_DMSC0_RAT_BASE + 0x60) = 0x00000000; //Region 4
*(unsigned int *)(CSL_WKUP_DMSC0_RAT_BASE + 0x70) = 0x00000000; //...
*(unsigned int *)(CSL_WKUP_DMSC0_RAT_BASE + 0x80) = 0x00000000;
*(unsigned int *)(CSL_WKUP_DMSC0_RAT_BASE + 0x90) = 0x00000000;
*(unsigned int *)(CSL_WKUP_DMSC0_RAT_BASE + 0xA0) = 0x00000000;
*(unsigned int *)(CSL_WKUP_DMSC0_RAT_BASE + 0xB0) = 0x00000000;
*(unsigned int *)(CSL_WKUP_DMSC0_RAT_BASE + 0xC0) = 0x00000000;
*(unsigned int *)(CSL_WKUP_DMSC0_RAT_BASE + 0xD0) = 0x00000000;
*(unsigned int *)(CSL_WKUP_DMSC0_RAT_BASE + 0xE0) = 0x00000000;
*(unsigned int *)(CSL_WKUP_DMSC0_RAT_BASE + 0xF0) = 0x00000000; //...
*(unsigned int *)(CSL_WKUP_DMSC0_RAT_BASE + 0x100) = 0x00000000; //Region 14
*(unsigned int *)(CSL_WKUP_DMSC0_RAT_BASE + 0x110) = 0x00000000; //Region 15

}

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AM6442: Error when M4 accss DDR using RAT