AM625: Questions Regarding Configuration of CP_GEMAC_CPTS0_RFT_CLK on AM6254A Using SDK 09.02.01.09

qingsheng Yin

Part Number: AM625

Dear TI Support Team,

I am currently working with the AM6254A processor and using SDK version 09.02.01.09. For reference, the documentation I’m following is titled "AM62x Processors Silicon Revision 1.0 – Texas Instruments Families of Products."

I would like to configure CPTS_RFT_CLK sourced from CP_GEMAC_CPTS0_RFT_CLK, and I have performed the following steps:

I configured the general-purpose register 0x000F41F0 for the CP_GEMAC_CPTS0_RFT_CLK pin A18 with the value 0x08254006, enabling the input function and setting the pin mux to CP_GEMAC_CPTS0_RFT_CLK.
Based on the requirements, I attempted to configure the CPTS_CLKSEL register to select CP_GEMAC_CPTS0_RFT_CLK as the input source. I also intend to feed in a clock signal ranging from 125MHz to 650MHz (I have an external PLL capable of outputting a sine wave within this frequency range).

I now have the following questions and would appreciate your guidance:

Are the above configuration steps feasible and valid for setting up CP_GEMAC_CPTS0_RFT_CLK as the source for CPTS_RFT_CLK?
If I input a 125MHz signal to CP_GEMAC_CPTS0_RFT_CLK, what are the required electrical levels and waveform characteristics (e.g., voltage standard, duty cycle, waveform shape)?
I was unable to locate the following registers or fields in the documentation:
- CPTS_CLKSEL
- CPTS_EN
- TS_PEND_EN
- ADD_VAL[2-0]
- The MODE[5] bit which is mentioned in the phrase: “64-bit mode is selected when [5] MODE bit set to 1h”
I did find references that may correspond to these:
- CPTS_CLKSEL might be CPSW_CKJSEL
- ADD_VAL[2-0] might correspond to CPSW_NUSS_VBUSP_CPSW_NU_CPTS_TS_ADD_VAL_REG
However, I could not find clear documentation for the others. Could you please confirm their correct register names and locations?
I came across the following forum post, which discusses using device tree configuration for AM64x:

TI E2E Forum Reference Post

In that post, AM64X_DEV_CPSW0 has mapped clock IDs. How can I identify or trace similar clock mapping IDs for the AM6254A in the device tree or TI SDK?
Are there any existing reference implementations or sample configurations available for using CP_GEMAC_CPTS0_RFT_CLK as the CPTS reference clock input?

Thank you in advance for your support and guidance.

Best regards,
TiAmo

3 个月前

0 Eirwen 3 个月前

TI__Mastermind 26475 points

Hello!

We have received your case and the investigation will take some time. Thank you for your patience.

0 Eirwen 3 个月前回复 Eirwen

TI__Mastermind 26475 points

Can you tell us a bit more about the usecase here? How are you planning to use the CPTS?

What OS is running on the A53 cores? I assume that you are planning on controlling the CPTS from the A53 cores.

0 qingsheng Yin 3 个月前回复 Eirwen

Prodigy 20 points

I am working on synchronizing the CPTS (Common Platform Time Sync) with an external reference on our AM6254A board, which runs Linux kernel 6.1.80 on the Cortex‑A53.

Currently, I have fed a 125 MHz square‑wave signal into CP_GEMAC_CPTS0_RFT_CLK and configured the relevant registers to route this to the rclk source. The input clock is recognized correctly by the system.

However, I need detailed criteria for the external clock to ensure reliable and precise operation. Specifically, I would like guidance or documentation on the following signal parameters:

Frequency tolerance (in ppm or ppb)
Jitter requirements, including cycle‑to‑cycle, phase jitter, and TIE jitter
Rise/fall time specifications (clock edge constraints)
Output drive strength and load matching requirements

I have not located device-specific specifications for the external CP_GEMAC_CPTS0_RFT_CLK input.

Could you please point me to the datasheet or technical reference that defines these electrical requirements? Alternatively, are there any validated reference designs or hardware test cases for CPTS external clocking that meet TI’s recommended criteria?

Thank you for your assistance.

Best regards,
TiAmo

0 Eirwen 3 个月前回复 qingsheng Yin

TI__Mastermind 26475 points

Based on your latest response, it sounds like you have set up your Linux system to source the CPSW clock from an external source.

Here are some additional tools that might be useful:

CLOCKTREE-AM62X (the AM62x CLock tree tool - useful for visualizing clock paths in the system and how registers should be set to get specific clock settings): https://www.ti.com/tool/CLOCKTREETOOL

Linux devicetree settings - clocks

If we want to set the CPTS to have a parent clock of CP_GEMAC_CPTS0_RFT_CLK, I would expect you to modify the Linux tree like this:

First, get the Device ID for the CPSW, and the Clock ID for the input clocks from the TISCI docs:
https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/am62x/clocks.html

From that page:
CPSW ID = 13.
Input clock CPTS_RFT_CLK = 3
Input parent clock to CPTS_RFT_CLK is CP_GEMAC_CPTS0_RFT_CLK = 6

Let's double check the current settings for CPSW and the CPTS clocks:
arch/arm64/boot/dts/ti/k3-am62-main.dtsi

        cpsw3g: ethernet@8000000 {
                ...
                clocks = <&k3_clks 13 0>; // CPSW ID = 13
                assigned-clocks = <&k3_clks 13 3>; // CPTS_RFT_CLK = 3
                assigned-clock-parents = <&k3_clks 13 11>; // PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK = 11
                ...
                cpts@3d000 {
                        ...
                        clocks = <&k3_clks 13 3>; // CPTS_RFT_CLK = 3
                        clock-names = "cpts";
                        ...
                };

So right now, both the CPSW peripheral, and the CPTS counter within the CPSW, are using CPTS_RFT_CLK as their clock source

Do you want the Ethernet CPSW peripheral to also use CP_GEMAC_CPTS0_RFT_CLK?

If yes, then you can just swap the assigned-clock-parents line. I would overwrite the value in your board-level dts file by adding a node like this. For example, you could add this to the bottom of k3-am625-sk.dts:

&cpsw3g {
        /* use CP_GEMAC_CPTS0_RFT_CLK as clock source for CPSW & CPTS */
        assigned-clock-parents = <&k3_clks 13 6>;
};

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AM625: Questions Regarding Configuration of CP_GEMAC_CPTS0_RFT_CLK on AM6254A Using SDK 09.02.01.09