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对C6748 GPIO的疑问

Other Parts Discussed in Thread: TMS320C6748

1.矛盾的描述:

1.1 SPRUH79A[10.5.22]

The PUPD_SEL settings are not active until the device is out of reset. During reset, all of the

CP[n] pins are pulled down. If the application requires a pull-up during reset, an external
pull-up should be used.

理解:复位期间内部下拉电阻有效,那么管脚状态应该为‘0’;复位后内部上拉电阻有效;管脚状态为'1'

1.2 SPRS590F –JUNE 2009–REVISED MARCH 2014 [6.4.1 Power-On Reset (POR)]

A summary of the effects of Power-On Reset is given below:
• All internal logic (including emulation logic and the PLL logic) is reset to its default state
• Internal memory is not maintained through a POR
• RESETOUT goes active
All device pins go to a high-impedance state
• The RTC peripheral is not reset during a POR. A software sequence is required to reset the RTC

理解:复位期间,管脚状态为'高阻';

以上描述矛盾?解释一下。

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2.GPIO的驱动能力在哪里有说明?

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测试电路1:

GPIO-------------|>---------[][][][](2k)------| gnd

复位期间不亮,但复位后LED微亮(比正常配置GPIO后亮度低),与1.1描述匹配。

测试电路2:

GPIO-------------<|---------[][][][](2k)------| vcc

在复位期间LED会闪一下(很暗,电流应该很小),与1.1描述匹配。

问题:

1.GPIO的驱动能力是否足够;

2.如何解决以上两个电路的问题。

  • 1. 以"During reset, all of the pins associated with these registers are pulled down"这个为准。下面的e2e上有提到。
    https://e2e.ti.com/support/dsp/omap_applications_processors/f/42/t/113556

    2. GPIO的驱动能力看数据手册第79页上的VOH, VOL, IOH, IOL。 
    http://www.ti.com/lit/ds/symlink/tms320c6748.pdf