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AM3352配置DP83848K问题

Other Parts Discussed in Thread: DP83848K

TI大神们,

    在下现在调试网络芯片DP83848K遇到问题,U-BOOT中调试修改如下:

   默认ID为0x01

static struct cpsw_slave_data cpsw_slaves[] = {
{
.slave_reg_ofs = 0x208,
.sliver_reg_ofs = 0xd80,
.phy_id = 1,
},
{
.slave_reg_ofs = 0x308,
.sliver_reg_ofs = 0xdc0,
.phy_id = 0,
},
};

board_eth_init()函数中设置了模式为mii

writel(MII_MODE_ENABLE, &cdev->miisel);
cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
PHY_INTERFACE_MODE_MII;

ping_mux中初始化为:

configure_module_pin_mux(mii1_pin_mux);

打印如下:
musb-hdrc: ConfigData=0xde (UTMI-8, dyn FIFOs, bulk combine, bulk split, HB-ISO Rx, HB-ISO Tx, SoftConn)
musb-hdrc: MHDRC RTL version 2.0
musb-hdrc: setup fifo_mode 4
musb-hdrc: 28/31 max ep, 16384/16384 memory
USB Peripheral mode controller at 47401000 using PIO, IRQ 0
musb-hdrc: ConfigData=0xde (UTMI-8, dyn FIFOs, bulk combine, bulk split, HB-ISO Rx, HB-ISO Tx, SoftConn)
musb-hdrc: MHDRC RTL version 2.0
musb-hdrc: setup fifo_mode 4
musb-hdrc: 28/31 max ep, 16384/16384 memory
USB Host mode controller at 47401800 using PIO, IRQ 0
Net: mac_lo===========d5b1
mac_hi===========7cb824ec
<ethaddr> not set. Validating first E-fuse MAC
PHY_INTERFACE_MODE_MII=======
maria: ++++++++++++++++++++++++++++++++++++++
maria: ++++++++++++++++++++++++++++++++++++++
maria: ++++++++++++++++++++++++++++++++++++++
maria: ++++++++++++++++++++++++++++++++++++++
maria: ++++++++++++++++++++++++++++++++++++++
phy_id: ----> ffffffff
PHY reset timed out
cpsw, usb_ether
Hit any key to stop autoboot: 0
U-Boot#
U-Boot#
U-Boot#
U-Boot#
U-Boot#
U-Boot# set serverip 192.168.1.1
U-Boot# set ipaddr 192.168.1.200
U-Boot# set netmask 255.255.255.0
U-Boot# ping 192.168.1.200
link up on port 0, speed 1000, full duplex
Using cpsw device
ping failed; host 192.168.1.200 is not alive

请问在u-boot代码中怎么读取以下 PHY 寄存器的值打印出来。

BMCR
BMSR
PHYIDR1
PHYIDR2
ANAR
ANLPAR
ANER
ANNPTR
PHYSTS 
FCSCR
RECR 
PCSR 
LEDCR
PHYCR 
10BTSCR 
CDCTRL1 
EDCR 

  • 可以直接在UBOOT代码里面打印:

    读取方法参考这里的函数:EZSDK_06_00_00_00/board-support/u-boot-2013.01.01-psp06.00.00.00/drivers/net/phy/phy.c

    146 int genphy_restart_aneg(struct phy_device *phydev)
    147 {
    148 int ctl;
    149
    150 ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
    151
    152 if (ctl < 0)
    153 return ctl;
    154
    155 ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
    156
    157 /* Don't isolate the PHY if we're negotiating */
    158 ctl &= ~(BMCR_ISOLATE);
    159
    160 ctl = phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, ctl);
    161
    162 return ctl;
    163 }