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66ak12 通过sysbios设置中断,core0能获取EventId,其他core不能获取

Other Parts Discussed in Thread: SYSBIOS

想要sysbios配置中断,以核减通信为触发原:

配置如下:

int32_t                 eventId;
     /* Get the event id associated with the host interrupt. */
     eventId = CpIntc_getEventId(9);
    /* Map the System Interrupt i.e. the Interrupt Destination 0 interrupt to the DIO ISR Handler. */
     CpIntc_dispatchPlug(CSL_CIC2_IPC_GR1, (CpIntc_FuncPtr)myCompletionIsr, (UArg)5, TRUE);
     /* Get the event id associated with the host interrupt. */
     eventId = CpIntc_getEventId(9);
     /* The configuration is for CPINTC0. We map system interrupt 112 to Host Interrupt 8. */
     CpIntc_mapSysIntToHostInt(2, CSL_CIC2_IPC_GR1, 9);
     /* Get the event id associated with the host interrupt. */
     eventId = CpIntc_getEventId(9);
     /* Enable the Host Interrupt. */
     CpIntc_enableHostInt(2, 9);
     /* Get the event id associated with the host interrupt. */
     eventId = CpIntc_getEventId(9);
     /* Enable the System Interrupt */
     CpIntc_enableSysInt(2, CSL_CIC2_IPC_GR1);
     /* Get the event id associated with the host interrupt. */
     eventId = CpIntc_getEventId(9);
     /* Plug the CPINTC Dispatcher. */
     EventCombiner_dispatchPlug (eventId, CpIntc_dispatch, 9, TRUE);
在core0 时候能插入,其他核运行不能插入。不能插入的原因是eventId  值为-1.
请问eventId  是怎么来的?在core0 运行时,从开始就能eventId  值就为 75,为其他core里面一直是-1
  • 因为在初始化的时候需要把时间和中断号绑定这样就能从中断号反查事件号,

    配置中断最好把底层的寄存器都看看,这样就知道哪些有配置哪些没有配置了。

    参考下述手册的中断控制器章节

    SPRUGW0 TMS320C66x DSP CorePac



  • 具体参见:

    系统事件映射表System Event Mapping — C66x CorePac Primary Interrupts

    事件号74对应的事件名 CIC_OUT8_PLUS_16_MUL_N,对应于核0为8,核1为8+ 16 = 24,核2为8+ 16 *2 = 40;

    对应为:

    核0下,取host interrupt 8 对应的事件编号是74,
    核1下,取host interrupt24 对应的事件编号是74,
    核2下,取host interrupt 40 对应的事件编号是74,

    核1下, 取host interrupt 8 对应的事件编号就没系统事件映射表里,自然返回为-1.也上针对cic0,cic1.

    系统事件映射表System Event Mapping 

     关于cic2输出描述不够详细,直说cic2输出8个shared events 给cores。但是系统映射表里面没有没有描述,相应的host interrupt 编号也没有。

    请问cic2输出8个shared events 及对应的host interrupt是什么?

  • 这应该是文档的问题,我确认之后再回复你

  • SRIO 事件INTDST0 能通过CIC0管理,触发中断,经过CIC2 确不行,理论是都是可以的,程序如下:

    CIC0 codes:
    /* Map the System Interrupt i.e. the Interrupt Destination 0 interrupt to the DIO ISR Handler. */
    CpIntc_dispatchPlug(CSL_CIC0_SRIO_INTDST0, (CpIntc_FuncPtr)myDioTxCompletionIsr, (UArg)hSrioDrv, TRUE);

    /* The configuration is for CPINTC0. We map system interrupt 112 to Host Interrupt 5. */
    CpIntc_mapSysIntToHostInt(0, CSL_CIC0_SRIO_INTDST0, 5);

    /* Enable the Host Interrupt. */
    CpIntc_enableHostInt(0, 5);

    /* Enable the System Interrupt */
    CpIntc_enableSysInt(0, CSL_CIC0_SRIO_INTDST0);

    /* Get the event id associated with the host interrupt. */
    eventId = CpIntc_getEventId(5);

    /* Plug the CPINTC Dispatcher. */
    EventCombiner_dispatchPlug (eventId, CpIntc_dispatch, 5, TRUE);

    CIC2 codes:
    /* Map the System Interrupt i.e. the Interrupt Destination 0 interrupt to the DIO ISR Handler. */
    CpIntc_dispatchPlug(CSL_CIC2_SRIO_INTDST4, (CpIntc_FuncPtr)myDioTxCompletionIsr, (UArg)hSrioDrv, TRUE);

    /* The configuration is for CPINTC0. We map system interrupt 112 to Host Interrupt 8. */
    CpIntc_mapSysIntToHostInt(2, CSL_CIC2_SRIO_INTDST4, 13);

    /* Enable the Host Interrupt. */
    CpIntc_enableHostInt(2, 13);

    /* Enable the System Interrupt */
    CpIntc_enableSysInt(2, CSL_CIC2_SRIO_INTDST4);

    /* Get the event id associated with the host interrupt. */
    eventId = CpIntc_getEventId(13);

    /* Plug the CPINTC Dispatcher. */
    // EventCombiner_dispatchPlug (109, CpIntc_dispatch, 13, TRUE);
    EventCombiner_dispatchPlug (eventId, CpIntc_dispatch, 13, TRUE);

    使用CIC2有什么要特别注意的,是否是CIC2出host interrupt 或是 evenid 有错?强行将event ID 设置为 109 也不能触发中断。

  • 请参考以下回复

    I have only 4 CIC2 events per corepac in the spec. Two are shared across all, each core gets two other unique outputs. So I think that the Figure is wrong. 

    #2: CIC_2_SPECIAL_BROADCAST is a generic way of referring to one of the unique outputs. For corepac N, the corresponding CIC2 output is as follows: 
    0 CIC2 output #[68]
    1 CIC2 output #[14]
    2 CIC2 output #[24]
    3 CIC2 output #[52]
    4 CIC2 output #[87]
    5 CIC2 output #[15]
    6 CIC2 output #[16]
    7 CIC2 output #[17]