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AM67A: Can the Cortex-R5 in the AM67A Main domain control a single screen display independently?

liutao shi
Prodigy 10 points
Part Number: AM67A
Other Parts Discussed in Thread: TDA4VM, AM67, AM62P

I understand that both AM67A and TDA4VM belong to the Jacinto series, and the Main domain has Cortex-A and Cortex-R5 cores. The Main domain can control the screen through DSS. Does this mean that the Cortex-R5 core in the Main domain can control a screen independently, thereby achieving a setup where RTOS and Linux control separate screens respectively, similar to a smart cockpit?

  • 0
    TI__Mastermind 36315 points

    Hi,

    We have received your post and the investigation will take some time. Thank you for your patience.

  • 0 回复 Taylor
    TI__Mastermind 36315 points

    Hi,

    R5F core is a part of MCU domain and not Main domain. With that said, it is still possible to share display between A53 and R5 cores. Please refer: https://software-dl.ti.com/jacinto7/esd/processor-sdk-linux-am67a/latest/exports/docs/linux/Foundational_Components/Kernel/Kernel_Drivers/Display/DSS7.html#driver-features .

    Note, there are 2 pipelines in one DSS. One pipeline can be controlled by A cores and the other by R5 core and later planes in these pipelines can be merged with overlay manager in the DSS.

  • 0 回复 Taylor
    Prodigy 10 points

    Sorry, I overlooked this point. The Cortex-R core of AM67A indeed belongs to the MCU Domain, while the Main domain of TDA4 contains the Cortex-R core. The link you provided does indicate that the remote core can send images to the pipeline, but I haven't found any related code examples. Moreover, the Technical Reference Manual of AM67 states that DSS only belongs to the MAIN domain. Could you please explain why this is the case?

  • 0 回复 liutao shi
    TI__Mastermind 36315 points

    Hi,

    Apologies for the confusion.

    The above portion is a bug in the SDK documentation and we do not plan to support display sharing on AM67A.
    May I know what the requirements are and why AM62P cannot be used?

  • 0 回复 Taylor
    Prodigy 10 points

    My requirements are similar to an intelligent cockpit. The specific details are as follows:
    1. The SoC supports the dual operation of RTOS and Linux/Android systems.
    2. It has two or more independent display screens.
    3. The RTOS kernel can independently control one screen display.
    Could you recommend a SoC with a relatively high cost-performance ratio for me?

  • 0 回复 liutao shi
    TI__Mastermind 36315 points

    Hi,

    Not sure if DL accelerator is a must for you. If not, AM62P is lower cost and supports your above mentioned points. (Refer: https://www.ti.com/compare-products/?id=3326&type=GPT&partList=AM62P,AM67A)

  • 0 回复 Taylor
    Prodigy 10 points

    I don't need DL. It would be even better if AM62P could meet my requirements. May I ask if there is an SDK or code available for AM62P that enables Cortex-R/M to independently control the screen display?

  • 0 回复 liutao shi
    TI__Mastermind 36315 points

    Hi,


    We do not have an example A53 and R5 running independent displays, but we do have the following examples:
    1. DSS Display Test : takes control of both pipelines within DSS0 and outputs through one VP (One display being controlled by R5, while other VP is not used)
    2. DSS Display Share : Single VP out is shared by A53 and R5 cores by each having control over different pipelines.

  • 0 回复 Taylor
    Prodigy 10 points

    Thank you for support,
    This is truly great news. According to your description, each DSS's two pipelines can be controlled by either Cortex-R or Cortex-A cores, or Cortex-R and Cortex-A can share one pipeline to achieve picture overlay. This is very flexible and meets all my requirements.
    1. Based on this calculation, I should be able to port LVGL to the Cortex-R's RTOS Project and push it to the screen through the pipeline for display. If this is possible, I will immediately order the AM62P_LP development board for testing.
    2. I have an AM6254 development board in hand. The difference is that the coprocessor has become Cortex-M. Can this achieve similar operations to AM62P? This chip has a more advantageous cost.
    3.The currently provided demos are all for the wakeup domain + FreeRTOS. Can the Cortex-R core in the MCU domain support the same operation?

  • 0 回复 liutao shi
    TI__Mastermind 36315 points

    We do not support RTOS based display on AM62x either from M4 or R5 core.
    There are some experimental (limited support on these examples) examples on AM62x A53 core with freeRTOS, that too with no support/example for display sharing among different cores.

    liutao shi 说：
    The currently provided demos are all for the wakeup domain + FreeRTOS. Can the Cortex-R core in the MCU domain support the same operation?

    We do not have software support for that and customer will need to port that on their own.

  • 0 回复 Taylor
    Prodigy 10 points

    Thank you very much for your support.
    Then I will exclude AM62X and use AM62P for development. I still have the following questions:
    1. Theoretically, the Cortex-R in the MCU Domain of AM62P should be able to control the screen display just like the Cortex-R in the Wakeup Domain, but there are no current examples. Does this mean that users need to manually port it? Is this understanding correct?
    2. Currently, all the DSS-related demos, after preparing the buffer to be displayed, send the display through FVID2 instead of using a simple framebuffer or the commonly used DRM in the Linux system. Is this to support the data stream from the camera at the same time?
    3. The Video pipeline of DSS is visible to both the Main Domain and the WKUP Domain. When using the Cortex-R core to control the screen display, do we need to disable the device tree description related to the display in the Linux dts?